SECTION I ORGANIZATIONAL AND INTERMEDIATE MAINTENANCE

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

SECTION I

ORGANIZATIONAL AND INTERMEDIATE MAINTENANCE

substitution of suitable test equipment,

6-7. GENERAL.

when the listed test equipment is not avail-

able, the test paramenters (characteristics)

6-8. The organizational and intermediate

and required accuracies for the test outlined

maintenance procedures described are di-

in this chapter are also given.

vided according to the Processor and Core

Memory acceptance test tapes (GINS I, II,

III, IV Test, Interrupt Test, Worst Pattern

PERFORMANCE TEST STA

6-11.

Memory Test, etc.). The procedures are

provided in the form of test tables that con-

6-12. The performance test standards com-

tain performance standards (TTY print outs

prise tests relating to the Processor and

or visual indications) which indicate that

Core Memory functions. These tests con-

a function is operating normally under the

tain performance standards which, if unob-

conditions specified.

tainable, isolate malfunctions to one or

more replaceable PC cards. The tests are

6-9.

MAINTENANCE SUPPORT EQUIPMENT.

accomplished by use of an Acceptance Test

Program (ATP) test tape. The test tape is

6-10. Table 6-l lists the test equipment

comprised of 12 functional tests and a

required to perform maintenance on the Pro-

utility program listed below:

cessor and Core Memory. To permit

Function

ATP Test

Basic operating system (BOS) program; a collection of

BOS

Programmer/Operator-oriented utility routines, and

a command processing monitor.

Performance test for CPA, CPU, and Bus Controller,

Part I.

Performance test for CPA, CPB, and Bus Controller,

Part II.

Performance test for CPA, CPB, and Bus Controller,

Part III.

Performance test for CPA, CPB, and Bus Controller,

Part IV.

Performance test for CPA, CPB, and Bus Controller

Interrupt.

Performance test for Core Memory and Core Memory

Controller, Part I.

Performance test for Core Memory and Core Memory

Controller, Part II.

6-3