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 T.O. 31S5-4-308-1
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
THEORY OF OPERATION
logic which may be defined in any of the
INTRODUCTION
following terms:
5 - 2 . This chapter contains information
MNE MONIC -N
MNEMONIC-P
which provides an understanding of the
functional principles involved in the oper-
MNEMONIC
MNEMONIC
ation of the Processor and Core Memory.
low
high
and tie-in of equipment. Section II de-
scribes functional operating circuit details.
logic 0
logic 1
to be true
to be true
chanical assemblies, is not applicable.
Illustrations referenced in this chapter are
zero volts
positive voltage
located in Technical Manual, Circuit Dia-
grams, T . O . 31 S5-4-308-3.
ground
open circuit
negative
5 - 3 . The circuits described in this chapter
voltage
use positive transistor-transistor-logic (TTL)
SECTION I
FUNCTIONAL SYSTEM OPERATION
which the data outputs, D000-P through
D017-P, will be read out of; or into which
ALL BLOCK DIAGRAM DESCRIPTION.
the data inputs, DI00-P through DI17-P, will
5 - 5 . The Processor and Core Memory
be written into. The DATA AVAIL-N Core
(figure 1) generates and receives data and
Memory output notifies the Processor that
control signals to and from the Alarm Control
the data outputs are present and ready to be
and VF Comm Link, TTY, VF Comm Link 1,
transferred. The MEM AVAIL-P output from
Formatter, Combiner Control Logic (CCL),
the Core Memory notifies the Processor that
Register Sender Junctor (RSJ), Rapid Memory
the Core Memory is available for further
Reload (RMR), RO TTY, and VF Comm Link 2.
instructions. The RD INIT-P, WT INIT-P,
The Processor processes these data and
FULL CYC-P, RD ONLY-P and MEM SEL-P
control signals which are stored in or read
outputs from the Processor determine the Core
out of the Core Memory. All operations per-
Memory mode of operation. The Core Mcm-
formed by the Processor are controlled by the
ory operates in two modes; the clear/write
software program stored in in the Core Memory.
mode and the read/restore mode. The
The Processor also receives the Clock timing
ZW1-P and ZW2-P inputs from the
and power fail inputs from the PFD/Clock
Processor cause the Core Memory to
function. The clock timing signal is used to
operate in the byte mode and determine
update the calendar and clock program stored
which byte of data, D000-P through D008-P
in the Core Memory. The power fail input
or D009-P through D017-P, is to be trans-
from the PFD/Clock function is used to notify
ferred to the Processor,
the Processor of an impending power failure
and causes an orderly shutdown of the Proc-
PROCESSOR FUNCTIONAL BLOCK
essor and Core Memory before power is re-
DIAGRAM DESCRIPTION.-
moved.
-
5-6. Address signals, AI00-P through AILS-P
5-8. GENERAL.
The functional sections
determine the Core Memory address from
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