RC Bus Driver

TM 32-5865-069-24&P

3-3.3.2.1 RC Bus Monitor. The RC bus interface circuit monitors the RC Bus wait-

ing for a data word addressed to the RSPU. Line receiver U31A buffers the RC BUS

STROBE . U31B buffers the RC BUS CLOCK signal. The signals are inverted by U8D

and U8E to provide the STROBE and CLOCK* signals. When the strobe sync logic cir-

cuit (U1C, U23B, U23C, U24A, U17A and U25A) detects STROBE*, it provides the RESET

COUNTERS* signal. This signal resets the frame counter (U32, U37) which then

begins to count CLOCK* signals. The frame counter feeds a seven-bit address to

the control signal generator (PROM U41). An eighth bit is provided by ADDRESS EN*

from U5B. U41 provides four control signals. These establish the timing for both

RC bus monitor and RC bus driver tasks. RC BUS DATA, buffered by U5A, is clocked

into serial-to-parallel converter circuit (U24B, U35). The address field in the

data word is compared with the unit address in U15. The unit address, COMPARE

ADDR A1-A5, is fed to U15 from PPI 0 (U29). When the address in the data word

matches the unit address, U15 produces an enable signal (A=B) which is fed to the

receive/transmit decoder circuit (U3D, U14A, U14B, U14C, U18D, and U6). STATUS

ENABLE* from U41 allows the decoder to check the logic of the sixth bit in the

data word. This bit determines if the RSPU is to transmit data onto the bus or to

receive data from the bus. The decoder provides either the RCV signal or the XMIT

ENABLE* signal. XMIT ENABLE* is used for the RC bus driver task, described in

para 3-3.3.2.2. The RCV signal enables data to be loaded into a First-In First-

Out (FIFO) shift register (U1B, U3A, U16A, U16B, U34, U36). The load function is

performed by control signal LOAD REG* from U41. The FIFO holds eight bits of the

data word at a time. The data is collected by the CPU using the CPU DATA BUS via

PPI 1 in 8-bit bytes. This action is controlled by the RD* and WR* signals fed to

the circuit. As each byte is loaded, the FIFO provides a RECEIVE INTR si nal for

the CPU.

3-3.3.2.2 RC Bus Driver. When the RC bus interface section is required to trans-

mit data onto the RC bus, the XMIT ENABLE* signal is active. This signal enables

the XMIT control logic circuit (U3B, U7A, U7B, U7C, U16D, U33B). This ci cuit de-

codes control and enable signals. The circuit provides TRANSMIT INTR and two con-

trol signals fed to parallel-to-serial converter U39. TRANSMIT INTR is fed to the

CPU to clock inhibit signal start the transmit routine. The two control signals

(BUS DRIVER DATA ACK*, and a signal) allow data to be parallel loaded into U39 and

then clocked out serially to the line driver (P/O U26). Data for this transfer

onto the RC bus is fed onto the CPU DATA BUS in eight-bit bytes. This data is

then fed to U39 via PPI 1 as BUS DRIVER DATA DO - D7. Control signal BUS DRIVER

DATA ACK* is used to load U39. BUS DRIVER DATA ACK* is also fed to the CPU, via

PPI 1. The signal informs the CPU that data is loaded. When the clock inhibit is

released, U39 clocks serial data out to the line driver (P/O U26). The line

driver drives the serial data onto the RC bus.

3-3.3.2.3 Control Interface. The CPU is interfaced with five control signal

inputs to PPI 0 and PPI

The signals, MONITOR ENABLE, ADDRESS GENERATOR

ENABLE*, and ADDRESS GENERATOR SELECT are used to allow the CPU to determine the

RSPU operating mode. The RCDU ADDRESS AO-A7 is bidirectional and used to collect

address bits for the data word, UNIT ADDRESS AO-A7 is hardwired to carry the RSPU

address. COMPARE ADDR Al - A5 for the RC bus monitor circuit are provided from

this input.

3-3.4 Control Sequencer CCA, (A9). Refer to figure 3-8, a functional block

diagram of A9. A9 provides the following functions: an address sequence for

micromemory A8; control of the IDDAT bus; the FFT processor clocks; A and B data

bus source decoding.

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