CIRCUIT CARD/MODULE FUNCTIONAL DESCRIPTION

TM 32-5865-069-24&P

fed to the CPD as the LOOK-THRU MODE CONTROL signal, A12 also uses this signal to

enable the control data word onto the CDAT bus and to provide the CIVLD flag.

When CIVLD is received by A9, the control word is decoded to determine a start

point for the sequence of addresses provided to microprogram memory A8. The

instruction sets, used to control the execution of the FFT programs, are stored in

read-only memory on A8. A9 addresses the memory using the UADDR bus. Various

signals, fed to the processor circuit cards from A8, control the data flow and

data processing operations. The processor starts by fetching data from A12

(ADISEL* enabling samples of the received signal onto the ADAT bus). Data is

stored in memory at addresses determined by the address output, MADDR, from AlO to

All. When WBIF signal processing is required, the RCVR BLANKING signal input to

A12 may occur before sampling is complete. A12 indicates invalid data by sending

PDBWTN to A7. This signal is transferred to the RCDU on RC Bus B. When sampling

is complete, A1O performs the required arithmetic operations on the stored data

according to instructions received from A8. AlO sends PROCESSOR STATUS flag

signals to A9. These are used to provide branch addresses to A8. A8 changes the

instruction set to meet the new requirement. The processor transforms the sampled

data into 128 spectral points. When the transform is complete, the data is stored

in memory, All. A8 then sends PIDLOAD* to A12 signaling A12 to collect the

transformed data from the BDAT bus. BDAT is collected and transferred to A7 under

the control of PICCLK and handshake signals from A7. When all the data has been

transferred, A12 outputs status flag DODONE to A9. CRSEL* resets this flag to end

the sequence.

3-2.5 Power Distribution. The ac power to the RSPU is applied to the three power

supply modules thru Electromagnetic Interference (EMI) filter A16, power on/off

switch S3 and three circuit breakers. Power supply modules are the encapsulated

non-repairable type with built-in regulation and over-current protection circuits.

The dc power supplies, +5V from PS1, +/-l5V from PS2, and +28V from PS3 are fed to

power monitor A17. A17 monitors the voltages from the power supply modules and

provides an indication (lamp in power ON/OFF switch) when all three are present in

the RSPU. The signal RSPU PWR STATUS is also provided to A6. In addition to the

main dc power supplies, -6 VDC is produced by the -6V regulator A21 for use on

A12. Over voltage protection for circuits using +5V is provided by VR1.

3-3. CIRCUIT CARD/MODULE FUNCTIONAL DESCRIPTION. The following subparagraphs

provide a functional description of the RSPU CCA/Modules.

3-3.1 Converter IF (A20). Refer to figure 3-6, a functional block diagram of

converter assembly A20. The inputs to A20 are the four WBIF (21.4 MHz) outputs

from RCVR 1-4 together with RCVR SELECT and ATTN SELECT control signals. The WBIF

signals are applied to a SP4T switch, S1. The selected signal is routed thru S1

by the control signal RCVR SELECT and fed to a switched 0-60 dB attenuator AT1.

The amount of attenuation is determined by the control signals ATTN SELECT. The

output from at1 is amplified by AR1 and filtered, to reject images and out of band

signals, by FL1. The IF signal is then down converted in mixer U1 using the 19.4

MHz local oscillator signal from Y1. The output of Ul, SELECTED IF, has a center

frequency of 2 MHz.

3-3.2 IF Down Converter (A14). Refer to figure 3-7, a functional block diagram

of IF down converter A14. The SELECTED IF signal input from A20 is fed via ampli-

fiers AR6 and AR5 to a power divider circuit. When a wideband signal is required,

the control signal WBIF* is active and enables amplifier AR2 in the upper leg of

the divider. The output of AR2 is fed thru a low-pass filter which has a cut-off

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