PROCESSOR DETAIL LOGIC DIAGRAM DESCRIPTION

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

5-114. READ/RESTORE MODE. The

are coupled through the sense amplifiers

read/restore mode reads information from the

which are enabled by SAS-P. The sense

core memory stack address and then returns

amplifiers outputs, SAOO-P through SA17-P

the same information to the same location

are coupled through the sense gates which

in the core memory stack. The read portion

are enabled by SAS1 -P and SAS2-P . The

of the cycle is initiated by the Processor

sense gates outputs, MDROO-P through

Core Memory Controller output signal

MDR17-P, are loaded into the data register

RD INIT-P going to logic 1 with the

by TDOX-P. DATA AVAIL-N now goes to

following conditions: WT INIT-P at

logic 0 indicating that the requested infor-

logic 0, RD ONLY-P at logic 0, and FULL

mation is available. Signals MDROO-P

CYC-P at logic 1. Under these conditions,

through MDR17-P now determine the level

timing and control logic signal AIX-P clocks

of DATA INHOO-P through DATA INH17-P.

address bits AIOO-P through AI15-P into the

The restore portion of the cycle is initiated

address registers. The outputs of address

when timing and control logic signal TINH-P

registers 00 through 12, MAROO-P through

is sent to the inhibit drivers, resulting in

the generation of inhibit current signals

MAR12-P, are applied to the address decod-

ing and switching circuits. Address bits

INHOO-N through INH17-N through the

AI13-P, AI14-P, and AI15-P are decoded by

cores in the core memory stack where a

the address registers 13, 14, and 15. The

logic 0 is to be restored. Write timing

outputs of the address registers 13, 14,

signals WTl-P and WT2-P are `now sent to

and 15, BSMOO-P through BSMO3-P, enable

the address decoding circuitry, resulting

the selected CM BSM. 50 nsec after AIX-P

in the generation of X and Y write currents,

as explained previously. Timing and con-

is generated MEM AVAIL-P goes low to

trol logic signal ME M AVAIL-P returns to

notify the Processor Core Memory Controller

logic 1 indicating that a new cycle may be

that the Core Memory is busy. RDR-P is

now generated which clears the data reg-

initiated.

ister. The timing and control logic circuits

now generate PRE YRT-P and MRT-P which

5-116.

PROCESSOR DETAIL LOGIC DIAGRAM

cause the control and buffer logic circuits

DESCRIPTION.

to generate XRTl-P, XRT2-N, and YRT-N.

This causes the address decoding and

5-117. GENERAL. The following paragraphs

switching circuits and X and Y current

contain the detail logic diagram discussions

sources to generate the appropriate X read

for the Processor functions. The Bus Control-

currents, XCAO-P through XCA7-P and

ler function consists of the service request

XSOO-P through XS15-P, and Y read currents,

selection and interrupt circuits and alarm

YCAO-P through YCA7-P and YSOO-N through

and INFIBUS timing circuits. The CPU con-

YS07-N, as determined by MAROO-P through

sists of the sequence register and control

MAR12-P. The X read currents cause cur-

storage circuit, microcode register circuit,

rent flow through one of the 128 X lines

control circuit, receive register circuit,

from the X diode matrix and the Y read cur-

transmit register circuit, address register

rents cause current flow through one of the

c i r c u i t , arithmetic logic unit (ALU) input

64 Y lines from the Y diode matrix. At the

multiplexer circuit, ALU circuit, register

cores where these lines intersect, if a one

file circuit, carry and overflow circuit,

was stored, core turnover occurs. Where

emulation instruction register circuit. ad-

a core turnover occurs a pulse is coupled to

dress recognition circuit, INFIBUS access

the appropriate sense line, S-00 through

circuit, and central timing circuit. The

S-17.

Core Memory Controller consists of the

command and page select circuit, address

5 - 1 1 5 . MSAS-P enables the data register to

transfer circuit, and data transfer circuit.

receive the output data, causes the control

The Autoload function consists of the con-

trol circuit, address recognition and ROM

and buffer logic circuits to generate SAS-P,

select circuit, INFIBUS access circuit, and

and causes the data register to generate

ROM and data circuit. The Parallel I/O

SASl-P and SAS2-P. Output signals S-00

function consists of the address recognition

through S-17 from the core memory stack

5-18