Power Supply Section

TM 11-6625-667-45/NAVSHlPS 0969-249-8010/NAVAIR 16-30APM123-9/TO 33A1-3-367-22

tains an emitter-follower stage and an amplifier

at least one reply pulse was not received. A re-

stage and is used to couple and invert the logic

ceived pulse is processed by the receiver section as

information. To eliminate repetition during basic

described in paragraph 2-4. During this test, if a

logic analysis, each type of logic circuit is de-

pulse is not received, read delay DS5 inhibits

scribed in a separate paragraph. Circuits that are

the receiver gate after 150 microseconds. A re-

essentially composed of nonlogic stages are de-

ceived pulse triggers video shaper DSS1, then the

scribed in later paragraphs in terms of stage

error blanking circuit and read delay DSS5 will

analysis

gate on the readout gate which, in turn, sets read-

out DFF5. The additional sequence of events is

a. Flip-Flop Multivibrators. All flip-flop multi-

described in paragraph 2-5e.

vibrators are bistable devices with one stage pro-

viding the 0-output and the other a 1 output. The

2-9. Power Supply Section

assignment of 0 or 1 to a stage is arbitrary, but

The power supply section contains a 28-volt dc

once established, it is carried through the text and

supply, + 12-volt dc supply, 12-volt dc supply,

illusrations. A conducting stage is considered to

and + 150-volt dc supply. The 28-volt supply is

provide a low output and a nonconducting stage

part of the front panel assembly (A15). The +12-

provides a high output. These conditions establish

volt and - 12-volt sources are located on module

the state of the flip-flop. A flip-flop state can be

A13, and the +150-volt supply is located on

selected by either a reset (c} or set input. In the

module A14. All supplies are fed by either the 28-

test set, these inputs are usually negative-going

volt supply or an external 28-volt input.. When the

voltages and may be either the lending edge or

test set is operating with a 115 volts alternating

trailing edge of an input pulse. By definition, a

current (ac) input, the 28-volt supply is switched

reset input is applied to a 0 stage and a set input

into the circuit. by 28 VDC-115 VAC-OFF switch

to a 1 stage, causing its respective output to go

A15S1. Its output. is connected to + 12-volt regu-

high because it stops the conduction of that stage.

lator module A13, + 150-volt power supply

Therefore, when a flip-flop is in a set state, its 1

module A14, and directly to the other test set

output is high and the 0 output is low. When it is in

sections. The 12-volt source is produced by a

a reset state, its 0 output is high and 1 output is

18-volt supply in module A14, which is regulated

low. (Note that the term reset used in this manual

by the 12-volt regulator.

is also known as clear.) Some flip-flops in the test

set have more than one reset or set input and also a

2-10. Basic Logic and Stage Analysis

trigger (or toggle) input. A trigger input causes

The test set contains both digital and nondigital

the flip-flop to assume the opposite state, regard-

circuits. Opeations performed by digital circuits

less of its present state. Figure 2-7 illustrates a

are described by means of basic logic circuit de-

typical flip-flop. The circuit stages are dc cross-

scriptions. Logic symbols and designations (MIL-

coupled by resistors R11 and R14. These resistor

STD-806B) are used in the supporting illusra-

and capacitors C6 and C7 provide the resistance-

tion, with associated switching also shown.

capacitance (rc) constant for switching time.

Circuit elements normally are not shown unless

With the flip-flop in the reset state, transistor Q3

they have special use. Logic circuits used in the

is biased off and not conducting. The collector (0

test set are conventional and all flip-flops, one-

output) potential is high (approaching the +1%

shots, diode ASD gates, and transistor gates are

volt dc input). This potential also holds the base

similar in design. The main differences between

of Q4 high through resistor R11, thereby holding

flip-flops are the number of inputs or outputs that

Q4 in n conducting state. Since Q4 is conducting,

its collector (1 output) potential is low (approach-

are used. The one-shots may prvide either one or

ing ground). This potential is coupled to the base

two outputs. Nondigital circuits, such as conven-

of Q3 by resistor R14 and Q3 is held at. cutoff. A

tional one or two-stage inverters ans emitter fol-

set input. (negative-going voltage) applied to C8

lowers directly associated with logic circuits, are

switches the state of the flip-flop. Transistor Q-1 is

not described in detail. A two-stage inverter con-

2-13