SECTION V THEORY OF OPERATION

T.O. 12P4-2APX-192

NAVAIR 16-35TS1843-1

TM 11-6625-1646-25

SECTION V

THEORY OF OPERATION

INDEX OF DIAGRAMS

Figure

Title

Page

5-1

Timing Diagram for Mode Generator (A2)

5-2

RAD TEST-MON switch of the control unit In MON position.

5-1. GENERAL.

(2) Simultaneously. when the switch lead to the power supply

5-2. This section contains the circuit description of the TS-

is grounded, one of the four input leads to mode enable NAND

1843A APX. The circuit description is divided into logic

gate (A2AlA) is grounded. A2A1A serves as an input enabling

discussion covering the In-Flight Test mode and Monitor

gate for the mode generator (A2). The output of A2A1A is

mode, and detailed circuit analysis of the various circuitry.

routed to A3Q8 of the reply evaluator circuitry which provides a

low path to ground for A3Q3 preventing operation of the

5-3. TEST POINT IDENTIFICATION.

monitor circuitry and allows RF transmission. The same

5-4. MAJOR TEST POINTS. The major test points of the TS-

output of A2A1A is simultaneously routed to the PRF enable

1843A APX are identified on schematic diagrams by a star-

NAND gate, A2A3A.

encircled arabic numeral. These major test points represent

5-9. At the same instant of time when the MODE 1 switch is

the primary inputs and outputs of the major assemblies of the

placed in the TEST position, the 400 PRF generator is

TS-1843A APX.

energized. The output of the PRF generator is inverted and

5-5. SECONDARY TEST POINTS. The secondary test points

then routed to the PRF enable NAND gate. The output of the

of the TS-1843A APX are identified on schematic diagrams by

PRF enable NAND gate is a trigger which triggers the clock

all encircled alphabetical character. These secondary test

gate, A2A4. A2A4 provides a low output to the test gate

points represent those primary test points which will enable a

control switch A3Q7 and a high output to the clock enable

qualified technician to effectively troubleshoot a particular

NAND gate, A2A3B. The 1 MHz clock generator, which was

circuit within an assembly.

energized at the same instant of time as the PRF generator.

5-6. LOGIC AND TIMING DIAGRAM ANALYSIS (See figures

provides an input for the pulse shaper amplifier A2Q3. A2Q3

FO-1 and 5-1).

provides the second input for the clock enable NAND gate

5-7. During the In-Flight Test mode of operation. the test set

which inverts the pulse. The negative transition of the output

generates interrogation pulse pairs In the desired mode and

of A2A3B is used to start the ripple-thru counter

applies this signal at a preset power level to the aircraft

(A2A5AA2A7B) counting.

transponder at a frequency of 1030 0.5 MHz. The test set

5-10. The ripple-thru counter is composed of five flip-flops

then analyzes the transponder replies to assure that the power

requiring a negative-going pulse (low) to trigger them. Each

level, reply center frequency. l)racket pulse spacing. reply

flip-flop triggers sequentially upon receiving a negative trigger

percentage. and the VSWR of the antenna circuit are all

from the preceeding flip-flop. The output of each flip-flop

above the preset minimum acceptable standard.

If all

forms a set of binary spaced pulses (figure 5-1) which are

parameters are within the preset limits, the test set causes a

routed to three time enable NAND gates A2A9A, A2A8C, and

TEST lamp on the external control unit to illuminate. indicating

A2A8A. The outputs of the time enable NAND gates along

a go indicator. If any of the above parameters are not within

with the outputs of the ripple-thru counter are routed to four

prescribed limits. the TEST lamp will not Illuminate indicating

mode selection enable NAND gates, A2A9C, A2AllA, A2AllB,

that a no-go (improper operation) condition exists. Since the

and A2A1B, a zero reference pulse enable NAND gate

basic operation of the In-Flight Test mode is the same for all

A2A1OA, sync enable NAND gates A2A3C, A2A3D, and

modes, the following functional discussion will cover only the

A2A2F, and a reset enable NAND gate A2A1OB. Depending

Mode 1 operation.

on the desired mode of operation, the associated mode

5-8.

Placing the RAD TEST-MON switch in OUT position

selection enable NAND gates and reference pulse enable

and MODE 1 switch on the control unit in the TEST position,

NAND gate will be enabled, thus providing an input to A2A9D

two basic functions are initiated: (1) Actuating the MODE 1

which inverts the signal. The high output of A2A9D is routed

switch to the TEST position grounds the switch lead to the

to the clock output enable NAND gate A2A1OC.

power supply and places the test set In an energized state.

This same action can also be accomplished by placing the

5-1