Figure 2-28. Universal Digital Patch Panel, Low Level Send Circuit (with Timing from Data Receiver to Data Sender), Schematic Diagram.

TM 11-5895-878-14&P

Figure 2-28. Universal Digital Patch Panel, Low Level Send Circuit (with Timing from Data Receiver to Data

Sender), Schematic Diagram.

From line equipment plugged

(2) When a patch cord plug is inserted into

the LINE jack, the following connections are made.

k. Low Level Send Circuit (with Timing from Data

Sender to Data Receiver), Program Module GP-10 (fig.

Terminal

Termination

From TCF equipment plugged

To TCF equipment plugged

(1) This programming module connects the

Terminated across 56K to

following terminals:

ground

B3 to J1

External timing

C1 to F3

(3) When a patch cord plug is inserted into

B1 to J3

the EQUIP jack, the following connections are made.

B2 to F1

Terminal

Termination

C2 to M1

POS hold battery

A1 to L3

Terminated across 56K to

A2 to H1

ground

D1 to K1

To line equipment plugged

D2 to K3

2-35