FUNCTIONAL DISCUSSION

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

The temporary inhibit signal is also applied as an error

This action selects the appropriate card address input on

signal to an input on the system priority encoder for

each of the card address multiplexers to produce the

processing. After the multivibrator's duty cycle expires,

card address output that is applied to the binary-to-BCD

the channel address counter is permitted to continue

converter. The 3-bit address select signals are also

counting.

This circuit configuration permits the

applied to the lamp display decoder logic to be decoded

diagnostic function to detect and identify more than one

into the appropriate indicator enable signal associated

channel out-of-tolerance condition over a given period of

with the card address being processed.

When

time. The maximum number of channel addresses that

multiplexer loss-of-timing signal MLOT- is applied to the

can be generated from the channel address counter is

priority encoder, a card address inhibit signal is applied

determined by the channel address comparator. The

to the card address multiplexers so that a card address

maximum number of active channels is applied to the

is not generated. The card address inhibit signal also

channel address comparator through maximum channel

causes the lamp display decoder logic circuits to decode

number signals CHMAXO through CHMAX3 applied

signal LMTIM that is applied to the front panel to light the

from the seq card. When the channel address output

LOSS OF MUX TIMING indicator. No card address is

from the channel address counter is the same as the

generated for signal MLOT- because the signal indicates

external channel address applied to the comparator, a

the absence of timing rather than a card malfunction.

reset (A=B) signal is generated from the comparator to

The same condition applies to demultiplexer loss-of-

the counter. The channel addresses from the counter

timing signal DLOT-, since no card address is associated

are also applied to inputs on the card address

with this error condition. All other error conditions

multiplexers to identify the channel card location for a

applied to the system priority encoder have card

given out-of-tolerance condition. End-of-scan signal

addresses associated with error signals.

MEOS3N1 from the OEG card is applied to the control

flip-flop to develop the clock signals that increment the

5-576. The card address outputs from the multiplexer

channel address counter, one time during each word

and demultiplexer channel card error detectors and the

period.

card address outputs from the multiplexer and

demultiplexer common card error priority encoders are

5-575. The system priority encoder has nine inputs;

applied to inputs on the card address multiplexers in the

each input has a priority status that is enforced when

card address encoder. When a 3-bit address select

simultaneous error conditions are indicated at two or

signal from the system priority encoder is applied to each

more inputs. An error signal to the priority encoder

of the multiplexers, one channel address input

causes the encoder to produce a 3-bit address signal

(associated with the error condition reported) is enabled.

that is applied to the five card address multiplexers in the

The card address is then routed through the multiplexers

card address encoder and to the lamp display decoder

in the card address encoder and is applied to the binary-

logic. The assignments to the inputs on the priority

to-BCD converter. The binary-to-BCD converter, in turn,

encoder are shown on the block diagram (figure 5-43).

converts the binary channel address into a BCD code

An error signal (other than signal MLOT-) applied to the

that is applied to the digital readout circuits on the front

priority encoder causes the encoder to generate 3-bit

panel.

address select signals to the card address multiplexers.

5-156