Serial Interface Test Function. - TM-32-5811-024-14-P0059

TM 32-5811-024-14&P

Figure 5-5 shows the key circuits that produce the serial output test code (DT DATA OUT) and its accompanying DT

STROBE OUT and DT CK OUT signals and shows the timing waveforms involved in this operation. The sequence

described in time state T0 thru T4 is initiated by setting the front-panel switch to SELF TEST/SEND (S18). The circuits

then respond as follows:

(1) Time state TO. Send latch U1A is cleared when switch S18 is pressed. The resulting low output (J1)

clears eight clock pulse counter U4 and loads the parallel-to-serial converter with the parallel (ASC/DLP) test code shown

in figure 5-4. Flip-flop U18 is also cleared by the low output of latch U1A.

(2) Time state T1, T2. When switch S18 is released, U1A is set. The resulting high output of send latch U1A

brings the parallel-to-serial converter to the shift mode of operation and sets start/stop flip-flop U3 one clock period later

(time T2). The high output of U1A also enables counter U4 and U4 begins counting the 500-kHz clock pulse input while

the high Q output (pin 9) of U3B enables differential driver U5A, providing a differential DT CLK OUT signal. In addition,

serial data are clocked out of the parallel-to-serial converter to differential driver U5B, providing the differential DT DATA

OUT signal.

(3) Time state T3. The output of the eight clock pulse counter (U4-11) drops when the 16th clock pulse is

counted. This negative transition clocks, since its Q output is high, and sets flip-flop U1B. The resulting high Q output

enables NAND gate U2C.

(4) Time state T4. Eight clock pulse counts later, the output of counter U4-11 goes high, driving U2C low at

pin 8. This low clears the START/STOP latch (U3) 24 clock pulses after the data output operation began in T1. The

cleared flip-flop (U3) disables clock output driver U5A (with a low Q output), and generates a differential DT STROBE

OUT signal via driver U13A.

d. DT MOD. A counter circuit consisting of U10, U11, and U12 divides the 500-kHz clock by 1024 to provide an

approximate 500-Hz clock. This 500-Hz clock is output via differential driver U13B to provide the DT MOD OUT signal.

This signal is looped to the DT MOD IN (pins 15 and 16) of CCA A5 and is used as the MUX SELECT signal during the

self-test operation.

Normal operation of CCA A5 is confirmed when the output of U22 (ANALOG 0 and ANALOG 1) reads 0 V dc when

the front-panel switch is in the HALF SCALE position and reads +2.5 V dc when the switch is in the FULL SCALE

position.

5-11. Serial Interface Test Function.

a. Unit-Under-Test Serial Interface Test. (see figure FO-12). Serial interface test CCA A6 tests the serial interface

CCA of the unit-under-test to verify proper operation. The test loads a 16-bit

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