FRONT PANEL DETAILED CIRCUIT DISCUSSION

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

5-610. When all the diagnostic error inputs applied to

signals UAO through UA3 from the display card. The

the display card are in a no-error state, the outputs from

combinations of digital displays that the signals develop

multiplexers No. 2 through No. 6 in the card address

are listed in paragraph 5-593. When LAMP TEST switch

encoder that are applied to OR gate U13-8 are high. In

S3 is pressed, the output from inverter U8-12 goes low

turn, the output from OR gate U13-8 to AND gate U22-8

and enables the LT input on drivers U3 and U4. This

at this time is a low inhibit signal. When the output from

condition produces a digital display of 88 from U1 and

one of the multiplexers goes high as the result of a

U2. Pressing the LAMP TEST switch also produces

secondary diagnostic error, the output from OR gate

lamp test signal LT and causes a high level signal to be

U13-8 goes high and enables AND gate U22. The result

applied to inverters U8-2, U8-4, and U8-6 to energize

is a count 22 and the MULTIPLEXER CARD indicator

relay K1 and light TEMPERATURE indicator DS11.

being lighted on the front panel.

When LAMP TEST switch S3 is released, signal LT is

removed and all indicators return to their normal state.

5-611. Self-test signal ST2goes high when the SELF

When the self-test mode of operation is initiated by

TEST switch on the front panel is set to the off (down)

setting SELF TEST switch S1 to the on (up) position,

position. At the same time, error reset signals ERST and

signal STS is applied to the ERD card to generate the

DERRS are applied from the ERD card to the display

self test signals to all cards. Ripple blanking input signal

card. Signal ERST is applied through OR gate U36-12

RBI- is generated on the display card and is applied to

and inverter U15-10 to clear flip-flop U17-6 and reset

the RBI input of U3. This condition produces a digital

counter U18 in the multiplexer circuits. This function

display of 00 from U1 and U2, When SELF TEST switch

permits the diagnostic circuits on the multiplexer cards to

S1 is on, a high input signal is applied to inverter U8-8 so

reset before the normal diagnostic function is resumed.

that the output from U8-8 goes low and energizes latch

Signal DERRS performs the same operation on the

temperature alarm relay K2. Relay K2, in turn, lights

demultiplexer diagnostic circuits (U17 and U9). Both

TEMPERATURE indicator DS11. Signal HOT- is applied

reset signals are also applied to the display card when

to electro-optical isolator AT1 and to diode CR1 when the

the DISPLAY RESET switch on the front panel is

power supply overheats. Signal HOT- applied through

pressed.

diode CR1 energizes and latches relay K2 to light

TEMPERATURE indicator DS11.

In turn, AT1 is

triggered into conduction to initiate signal IPSE that turns

5-612. FRONT

PANEL

DETAILED

CIRCUIT

off the power supply when the TEMP SHUTDOWN

DISCUSSION.

jumper is installed on the front panel. Signal IPSE

remains on until the POWER CONTROL ON/OFF switch

5-613.The following discussion is based on the front

S4 is set to OFF and then back to ON. When the TEMP

panel schematic diagram in the circuit diagrams manual.

SHUTDOWN jumper is not installed, an overtemperature

The FAULT LOCATION digital display consists of 7-

condition does not shut down the power supply but the

segment optoelectronic display units U1 and U2. The

TEMPERATURE indicator lights. When the SELF TEST

displays are controlled by BCD-to-segment decoder/

switch is set to the off position, or the lamp test switch is

driver units U3 and U4. In normal operation, the tens

pressed and then released, reset temperature alarm

digital display (U1) is controlled by the outputs from

signal RTA is applied through inverter U8-10 and

driver U3, which, in turn, is controlled by tens address

unlatches relay K2 if it is in the latched state.

signals TA0 and TA1 from the display card. The units

digital display (U2) is controlled by the outputs from

driver U4, which, in turn, is controlled by units address

5-166