Error Rate Detector (ERD) Circuits - TM-11-5805-688-14-10245

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

The minor frame count in the overhead data bits is

maintain a count greater than eight. When the count

contained in words 24 through 28. There- fore, an A=B

decreases to a count of seven, the count 8- signal is

output can only be obtained during a compare in word

routed to the error reset circuits, which, in turn, generate

28. An output from the minor frame comparator can only

a demultiplexer error reset signal. When the counter

be accepted by the AND gates in the input of the error

output reaches zero, the resynchronization of the minor

up/down counter during the time that word 28 signal

frame counter is performed.

DW28 and end-of-scan signal DEOS2B- are applied to

the AND gates. Therefore, when a compare is made

5-541. Error Rate Detector (ERD) Circuits (Figure FO-

during word 28, an A=B (high) output becomes a count

10). The ERD circuits monitor the rate at which data bit

up input to the error up/down counter. When a no-

errors occur in the incoming high-speed serial data

compare exists during word 28, the absence of the A=B

stream. When the detected error rate exceeds a

signal is a count down input to the counter. When the

predetermined threshold, the ERD circuits cause the

error up/down counter is decremented to produce a

front panel LINK ERROR RATE indicator to light.

count zero, a preset enable signal is applied to the

Detection of data bit errors requires a knowledge of what

counter control. The counter control, in turn, presets the

sense (1 or 0) the data bits should be, as well as what

existing minor frame count (during word 28) in the

sense the data bits actually are. Of all the data bits

overhead shift register into the minor frame counter to

entering the demultiplexer, only the correct sense of

reestablish synchronization. The minor frame counter

selected overhead bits in the three stuffing codes is

continues to generate sequential minor frame counts

known.

Therefore, error rate measurement is

DMFCO through DMFC4 until another preset enable

accomplished by using a statistical sampling approach in

signal is generated by the error up/down counter.

which the rate of errors occurring in the overhead data

bits is considered to be representative (within statistical

5-540. When the equipment is initially energized, the

limits) of the error rate occurring among all data bits

minor frame count in the 5-bit overhead register does not

received. More specifically, errors detected in overhead

match the minor frame count from the minor frame

data bits 1 through 23 by the FS card are used by the

counter. Therefore, each output from the minor frame

ERD card for error rate measurement purposes. Three

comparator during word 28 decrements the error

sets of error counts from the FS card are applied during

up/down counter until a preset enable signal (count zero)

word 28 to the three error count (1, 2, and 4) selectors

is generated and applied to the counter control circuit,

on the ERD card. At the same time, the decoded stuff

which, in turn, causes the minor frame count from the

command code (positive,

negative, or no action),

overhead register to be pre- set into the minor frame

represented by the presence or absence of signals

counter. Therefore, the two minor frame counts applied

DNSE and DPSE, selects one set of error counts to be

to the minor frame comparator at the next compare time

applied through the three error count selectors to the

should be the same. In the synchronous condition, the

overhead error counter. When signal DPSE is applied

error up/down counter is incremented until it contains a

error count signals DEPSO, DEPS1, and DEPS2 are

maximum count of 15. When a count of 15 is reached,

applied to the preset inputs of the overhead error

AND gate U19 inhibits a further count up condition. In

counter.

normal operation, the error up/down counter should

5-144