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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
The fixed 11-bit command code applied to the B inputs
This is checked in the serial sync acquisition and sync
of each comparator is shown on the logic diagram in the
maintenance circuits,
circuit diagrams manual. The odd data bit numbers (1
through 9) programmed into the code comparator are the
5-525.  At the time that the parallel sync acquisition
reverse of the bit numbers listed on the code diagram (0
circuits generate signal DSYNC-,  word reset flip-flop
is 1 and 1 is 0). This is to compensate for the barred
U61-9 generates demultiplexer reset signal DWPR- that
odd-numbered signals applied to five of the A inputs to
is routed to the GC/DM card to preset the word counter.
the code comparator. When a compare is made, the
While signal DWPR- is being generated, the output from
A=B signal from the code comparator is applied to one of
OR gate U51-4 generates a reset signal that resets the
the compare latches in U54. When a compare is made,
three bit error counters (U42, U43, and U44). When
one of the outputs from U54 is applied to OR gate U53
the circuits operate in the sync maintenance mode, the
and to one input of parallel sync latch U62. In turn, the
reset signal from OR gate U51- 4 is also generated when
output from OR gate U53 is applied to sync enable flip-
signals DEOS2- and DW29- are applied to AND gate
flop U56 and to one input of AND gate U55. When the
U50-4 at the same time.  Word 24 through 29 signal
next RIO- signal occurs, AND gate U55 latches U62 so
W2429 is applied through OR gate U36-6 to prevent the
that a signal is applied through OR gate U53 as the
three bit error counters from further counts in the data
parallel sync (PS) signal.  The parallel sync signal is
word after word 23 in each minor frame period.
routed through OR gate U52 to disable latch U54 by
holding it in a reset state. The signal is also routed as an
enable signal to one input of AND gate U60 in the serial
5-526. Data bits SD3 from U13-7 are clocked into data-
sync acquisition circuits. When flip-flop U56 is clocked
in flip-flop U61-5 by end-of-scan signal DEOS2 and
by the next RIO- signal,  demultiplexer sync signal
system clock RIO-. When the demultiplexer is in frame
DSYNC- is generated for one bit time. At the time that
synchronization,  the data bits (SD3) clocked through
latch U62 is latched, the appropriate NAC enable, PSC
U61 are bit 0 of each applied data word. The serial SD3
enable, or NSC enable signal is applied as an enable
data bits clocked through U61-5 are applied in parallel to
signal to one input of an AND gate (U60-8, U59-8, or
one input on three exclusive OR gates U45. Each of the
U59-12) associated with the appropriate bit error counter
three exclusive OR gates receives one of the three serial
in the serial sync acquisition circuits. The appropriate
sets of stuff command codes (DPSC,  DNSC,  and
enable signal is selected by the signal applied through
DNAC) from the GC/DM card.  When the bits do not
latch U54 from the comparator that generates the A=B
compare, the appropriate OR gate generates a high-
signal.
level error signal (clock) during bit 0 to appropriate error
bit counter U42, U43, or U44. The data check in the
5-524. Once signal DSYNC- is generated, the timing
serial sync acquisition function starts with bit 0 of data
circuits in the demultiplexer are synchronized with the
word 12.  The output from data-in flip-flop U61-6 is
incoming data timing and the overhead stuff codes
applied as demultiplexer overhead data signal DOD- to
contained in bit 0 of the incoming data message should
the GC/DM card during bit 0 of each data word.
form a compare with the equivalent bits in one of the
three stuff command codes generated on the GC/DM
5-527. Only one bit error counter (U42, U43, or U44)
card and applied to the FS card.
output is enabled during the serial sync acquisition
function.
5-139

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