VLSR Block Diagram Discussion

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

5-499. When the LSB of the ports in use signal

per- formed on SD2 and SD3 data bits applied to the

(DPUBO) from the seq card is a 1, the VLSR operates in

other R.A.M.'s in the VLSR. Each of the data bits

the mode that processes an even number of data bits

latched into the storage registers is also applied to the

when n+l is an even number (18, 20, 24, etc). At this

A1, B1, A2, or B2 input of a data selector. There are

time, the odd-bit circuits are inhibited. The half-rate

five data selectors in the VLSR, each generating two bits

clock generator is clocked by system clock signal RIO-

of the 10-bit parallel output (B1 to B10) to the stuff

and produces the half-rate clock signals applied to the 4-

command code comparators. The A and B select

bit ad- dress counter and the parallel storage registers in

signals applied to the data selector are programmed to

the primary shift register. When the count (4-bit address)

alternately select A1 and B1 inputs for out- put signal B1,

from the counter reaches the count contained in signals

and A2 and B2 inputs for output signal B2. Each output

DPUB1 through DPUB4 applied to the address

is enabled for one system clock RIO time. The result is

comparator, an A=B condition is generated to produce

that consecutive data bits for a given data word

the signal that presets the 4-bit address counter out- put

configuration appear at the B1- output and consecutive

to a count of zero. For example, an RIO of 2400 kHz

data bits, delayed one data word, are produced from

produces 4-bit ad- dress signals to R.A.M.'s No. 1

the B2 output.

through No. 5 at a rate of 1200 kHz.

5-500. The five R.A.M.'s in the primary shift register are

5-501. When the LSB input of ports-in- use signal

identical. Each R.A.M. performs a read and write

DPUBO from the seq card is a zero, the VLSR operates

function for two pairs of parallel SD2 and SD3 data

in the mode that processes an odd number of data bits

inputs. Each of the four data inputs has a maximum of

when n+l is an odd number (19, 21, 25: etc). At this

16 memory locations in a R.A.M. to process up to 16

time, the circuits that generate the odd bit are enabled to

odd- or even-numbered data bits in a given data word

process the odd data bit that is added in series with the

application. In normal operation, the first pair of SD2

data bit output from the primary shift register. The

and SD3 is combined and becomes output B1 and the

circuits specifically associated with the odd-bit logic are

second pair of SD2 and SD3 is combined and becomes

identified on the block diagram in figure FO-8 by heavy

output B2 from the VLSR. When the half-rate clock-

lines. The odd-bit function is enabled when the 4- bit

signal from the half-rate clock generator is applied, the

address counter produces the maxi- mum count

4-bit address counter is incremented one count and the

necessary to generate an A=B output from the address

next sequential address is applied to the five R.A.M.'s.

comparator. The AND gate produces an enable signal to

At this time, the R.A.M.'s have read signals applied.

the odd-bit control circuit when the A=B and the half-rate

When the half-rate clock signal is generated, the

clock- signal are present. The odd-bit control circuit

storage register latches the four data outputs from the

generates an inhibit signal that delays the next

R.A.M. An instant later, the write enable signal-is

generation of the R.A.M. read and write signals for two

applied to the R.A.M. and the parallel SD2 and SD3 data

RIO times while the odd data bit from each odd bit shift

bits applied to the DO and D1 inputs are written into the

same address that was just read. In turn, the SD2 and

inhibited in the primary shift register function, the odd-bit

SD3 data bits latched into storage register locations 1D

address select flip-flop produces a clock signal that

and 2D are applied to the second set of D2 and D3

clocks in the data bit (SD3-) applied to odd-bit shift

inputs of the same R.A.M. and are written in the

equivalent memory locations. This operation is serially

5-132