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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
Since pairs of data bits are applied and stored at the
shift register, assume that a 24-bit word is used. Only
one-half RIO rate,  over a period of 16 write enable
the first 12 memory locations associated with the four
commands, the two inputs contain the maximum (n+1 =
data inputs DO through D3 are addressed.
After
32) consecutive data bits of a given data word. The logic
memory location 12 is addressed, the 4-bit address is
application permits the VLSR to operate at a desirable
truncated and the next memory location ad- dressed is
slower rate that is one-half the rate (Ro) at which the
location 1. In this configuration, a 24-bit delay exists
incoming data stream is applied to the demultiplexer.
between the data bit for a given memory location
associated with inputs DO and D2. There- fore, the data
in the parallel memory locations associated with inputs
DO and D2 or D1 and D3 are always delayed one word
time (24 bits) apart. The truncation occurs when the 4-
5-489. When the write sequence is generated, the four
bit address is the same binary code that is applied to the
data bits being read out of four parallel memory locations
address comparator using ports- in-use signals DPUB1
in the R.A.M. are latched into the storage register just
through DPUB4.  The A=B compare signal from the
before the write function occurs in the R.A.M. Therefore,
address comparator resets the 4-bit counter output to
when the write enable signal occurs, the data bits read
zero when N+l is an even number.
out of the memory locations associated with inputs D0
and D1 are written into the same memory locations
5-491.  The four parallel data bits applied through
associated with inputs D2 and D3.
The memory
storage register No. 1 to the A and B inputs of data
locations associated with inputs D0 and D1 write in the
selector No. 1 are always from the same row of memory
incoming SD3 and SD2 data to the VLSR. This almost
locations (DO, D1, D2, and D3) in the R.A.M. In turn,
instantaneous write/read sequence causes the data bit
the A and B inputs are alternately selected at the RIO
written into the parallel memory location associated with
rate. Therefore, the outputs from both B1 and B2 will be
input D0 to be delayed one data word time from the data
a sequential readout in the same order in which serial
bit being written into the equivalent data bit associated
data bits were originally applied to the data shift register
with input D2. In turn, the SD2 data written into the D1
in the sync acquisition circuits.  Also,  the bit delay
memory location is delayed one data word time from the
between the bits in B1 and B2 are always one word time
data bit written into the equivalent D3 memory location.
apart.  For example,  while the B1 outputs are bit
As shown in figure FO-7, for example, the data bit in
numbers 1, 2, 3, 4, 5, 6, 7, the B2 outputs are bit
memory location 5 for input D0 is bit 9. In the next write
numbers 1, 2, 3, 4, 5, 6, 7. This illustrates the 32-bit
cycle, bit 9 is read out and written in the same memory
delay when the equipment is configured for a 32-bit data
location (bit 9) for input D2. This is a 32-bit, or one word
word.
time, delay for an equipment application using an n+1 of
32.
5-492. The 3Q and 4Q outputs from the storage register
are applied in parallel to DO and D1 on R.A.M. No. 2 in
the VLSR. The procedures are repeated again in R.A.M.
5-490.  During normal operation in a 32- bit word
No. 2 and storage register No. 2 to establish B3 and B4
application, the 4-bit address is truncated after memory
outputs and provide an additional two-word (words 3 and
location 16 is addressed and the next memory location to
4) delay.
be addressed is location 1. To show the versatility of the
5-128

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