Overall FS Card Discussion

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

The parallel sync control circuits, in turn, generate de-

At this time, enable signal PSC, NSC, or NAC applied

multiplexer frame sync signal DSYNC-, parallel sync

to the selected error counter is also removed.

enable, and one of the enable signals (PSC, NSC, and

NAC). Signal DSYNC-, which lasts one data bit time, is

5-479. Signal DFS indicates that the sync acquisition

generated to initiate demultiplexer timing signals so that

function is complete and the serial sync acquisition and

bit 0 of word 12 in each of the stuff code commands

sync maintenance circuits are performing the frame sync

(DPSC, DNSC, and DNAC) is applied to the FS card at

maintenance function. In the frame sync maintenance

the same time that bit 0 of word 12 in the incoming data

function, bit 0 in words 1 through 23 of each minor

stream (MDS-) occurs. Signal PSC enable, NSC

frame is compared against the same bit in each of the

enable, or NAC enable and the parallel sync enable

three stuff command codes applied from the GC/DM

signals enable the serial sync acquisition function in the

card. The serial overhead message in bit 0 of words 1

serial sync acquisition and sync maintenance circuits.

through 23 of the incoming data (MSD-) is applied to the

Signal DSYNC- is also applied as a reset signal to the

three active code comparator-error detector circuits. At

three bit error counters in the serial sync acquisition and

the same time, one of the three stuff code commands

sync maintenance circuits.

generated in the GC/DM card is applied to each of the

three circuits. When frame synchronization is proper,

5-478. In bit 0 of words 1 through 11, the appropriate

one of the three bit error counters contains an error

stuff code command has been determined and an

count of seven or less and enables a count up output

enable signal has been applied to the appropriate bit

through an OR gate to the error up/down counter. In

error counter. Therefore, when signal DSYNC- is

normal operation, the other two bit error counters

initiated and the timing circuits in the demultiplexer circuit

associated with the two stuff commands not in a given

are synchronous with the incoming data stream, only

overhead message produce a maximum error count

one of the three code comparator-error detectors in the

output. All three bit error counters must contain an error

serial sync acquisition and sync maintenance circuits is

count of eight or more during a given minor frame period

enabled to perform a valid serial compare of bit 0 in

to produce a count down input through the OR gate to

words 12 through 23 (B12 through B23). When proper

the error up/down counter.

The up/down counter

frame synchronization is obtained,

the appropriate

prevents a loss-of-frame status when a limited number of

(positive stuff, negative stuff, or no action) code

overhead data bits is missing or incorrect in the compare

comparator-error detector should detect less than three

function. At the end of each minor frame period, word

errors while monitoring bit 0 in words 12 through 23. If

29 signal W29 resets the bit error counters to a count of

three or more errors are detected, an error reset signal

zero for the next compare function performed in the next

is generated to restart the parallel sync acquisition

minor frame period.

function. When frame synchronization is maintained

through word 23, word 28 signal W28 removes the

5-480. The error up/down counter is initially set to a

parallel sync enable signal and produces demultiplexer

count of five at the end of the sync acquisition phase.

frame sync signal DFS from the control circuits.

The maximum count retained in the counter is a count of

five. When a count up signal is applied to the counter

during word 28 of each minor frame period, the counter

only counts up when it contains a count between one and

four.

5-124