DETAILED CIRCUIT DISCUSSION - TM-11-5805-688-14-10221

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

5-451. Figure 5-21 illustrates the relationship of the data

U4-10, U5-10.The data bits are clocked into the shift

pulses to the reconfigured analog signals. The figure

also shows the filtered analog signal superimposed over

inverter U7-6 to the shift register. The data bits (bit 1) in

the reconstructed analog signal output from the

the shift register are applied through inverter U7-2 to the

integrator. The filtered analog signals from the bandpass

base circuits of negative inhibit switch Q2 and positive

filter circuit are applied to the output amplifier-drivers

inhibit switch Q3. When the output of the inverter is low,

circuit. The output amplifier-drivers circuit, in turn,

Q2 is enabled and effectively grounds the negative

amplifies and produces the balanced voice channel data

output from slope control U3-10 to the negative input (pin

output signals DOXX and DOXX-.

7) of U2-10. The condition allows the positive drive

voltage from slope control amplifier U3-12 to drive

integrator U2-10. In turn, a high output from U7-2

5-452. Diagnostic Circuits. The error detector circuit

enables positive inhibit switch Q3 and effectively grounds

samples voltage levels from the bandpass filter and the

the positive output from slope control amplifier U3-12 to

output amplifier-drivers circuit. The circuit configuration

the negative input of integrator U2-10. In turn, this

is such that a failure in one area causes most of the

condition allows the negative drive voltage from slope

circuitry to saturate in one direction. When a circuit is

control U3-10 to drive integrator U2-10. Therefore, the

faulty and a saturation condition occurs, an error signal

output from U2-10 varies in relationship to the polarity of

is applied to the diagnostic control circuit. The diagnostic

the drive voltages applied to input pin 7 from U3-10 or

control circuit, in turn, generates card error signal on

U3-12.

the positive stuff request (DPSTXX-) line unless an

inhibit signal is applied to it from the loss-of-data

5-456. The Q and Q outputs from the 3-bit shift register

multivibrator or from the delay start multivibrator. The

are applied to AND gates U6-6 and U6-12 in the decoder

loss-of-data multivibrator is a retriggerable one-shot

logic. When the three Q outputs or the three Q outputs

multivibrator that is held in conduction by the incoming

are all high, one of the two AND gates is enabled and

data pulses. When the data pulses are missing, the

produces a signal through inverter U7-12 that biases Q1

multivibrator duty cycle expires and an inhibit signal is

off in the slope control circuit. This condition drives the

produced to prevent the generation of an erroneous card

voltage applied to pin 7 of U3-10 more positive. In turn,

error signal. The delay start multivibrator generates an

the output from U3-10 goes more negative and the

inhibit signal to the diagnostic control circuit for 2.7

output from U3-12 goes more positive. Therefore, the

seconds when the VD card is initially energized. The

positive or negative drive applied to pin 7 of U2-10, in

inhibit signal prevents an erroneous card error signal

turn, causes the integrator output voltage to vary with an

from being generated when the equipment is first turned

increased (positive-going or negative- going) slope effect

on and when data and timing signals are absent.

on the reconstructed analog signal being developed. As

soon as the decoder logic detects the condition wherein

5-453. DETAILED CIRCUIT DISCUSSION.

the three bits being monitored are not all zeros or ones,

Q1 is biased back into conduction, reducing the dc bias

5-454.Functional Circuits.

level to pin 7 of U3-10.

5-455. The incoming channel data pulse DTIX- are

applied through inverter U7-4 to 3-bit shift register U4-6,

5-120