DETAILED CIRCUIT DISCUSSION - TM-11-5805-688-14-10188

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3010

OR gate U12 sets the composite error flip-flop, which

one of the four comparators and one of the four A=B

generates data mux diagnostic error signal MDM to the

inputs to AND gate U9 goes low and sets the gated clock

display card.

Exclusive OR gate U23 effectively

error flip-flop to generate diagnostic gated clock error

compares the MSD output from the functional data

signal MGC that is applied to the display card. The

multiplexer circuits with the MSD output from the

gated clock error flip-flop can be set and reset by signals

diagnostic data multiplexer circuits. The diagnostic data

ST2and ERST as explained in paragraph 5-328.

multiplexer circuits are identical to the functional data

multiplexer circuits and produce identical but

5-330. DETAILED CIRCUIT DISCUSSION.

complementary MSD and MSD signals. Therefore, in

normal operation, MSD and MSD are complementary to

5-331. Format Generation Function.

each other and make exclusive OR gate U23 produce a

high-level (no error) signal to OR gate U12. If one of the

5-332. The word counter, consisting of flip-flop U5 and

two inputs to the exclusive OR gate malfunctions,

binary counter U14, is incremented by end-of-scan signal

exclusive OR gate U23 produces a low-level error signal

MEOS2B to produce 5-bit binary word counts WCO

so that signal MDM is generated. Self-test signal

through WC4 that address read only memory (ROM)

ST2sets the composite error flip-flop for an error

U20. The word counter counts sequentially until it is

indication when the SELF TEST switch on the front panel

reset by word count 29 from flip-flop U3-7 in the words

is set to the on (up) position. Error reset signal ERST

28/29 generator. In the multiplexer function, preset

resets the flip-flop when the SELF TEST switch on the

inputs P1 and P2 on binary counter U14 are set to 00 by

front panel is set to the off (down) position or the

the application of signal M+5R through inverter U15.

DISPLAY RESET switch on the front panel is pressed.

This configuration I)resets the word counter to a count of

1 after word 29. In the demultiplexer function, word

5-329. Gated Clock Error Detection Circuits (Figure

counter preset signal DWPR is applied one time to

5-26). In normal operation, four gated clock comparators

inverter U15 when synchronization is initially obtained in

sample gated clock signals MGCO1 through MGC15 (A

the frame sync card. Signal DWPR sets the P1 and P2

input) from the gated clock generation function against

inputs on binary counter U14 to 11 and also applies a

the same signals (B input) generated by the diagnostic

preset signal through OR gate U4, and inverter U13,

gated clock generation circuits. The diagnostic gated

presetting the counter to a count of 12. After initial reset

clock generation circuits are identical to the functional

in the demultiplexer function, the word counter is preset

circuits and produce gated clock signals that normally

to a count of 1.

are identical to those produced by the functional circuits.

When a malfunction occurs, a mismatch is detected by

5-333. The ROM is programmed to generate six outputs

that are selected by 5-bit word count signals WCO

through WC4 applied from the word counter. As shown

in table 5-5, the ROM outputs are two identical sets of

the three stuffing codes (PSC, NSC, NAC for the

functional circuits and PSCD, NSCD, NACD for the

diagnostic circuits).

5-87