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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3010
dependent on the individual system requirements. Port
5-274. As the port scan counter is incremented, the
assignments are in sequential order.  For example, a
active port mux sequentially interrogates the PORT
system configuration using 20 ports will use the first 20
STRAPPING switches. When an active channel port is
ports (ports 1 through 20); ports 21 through 31 are not
interrogated, a count is multiplexed through the active
used.
port mux to increment the active channel counter. The
active channel counter is not incremented when the
5-271. The PORTS IN USE switches control the length
active port mux interrogates a port that is in the S
of each scan (number of active ports interrogated) in a
strapped configuration. When a scan is completed, the
word format by controlling the maximum number of
active channel counter should contain a binary address
active ports in the system configuration. A 5-bit binary
count that is equal to the number of active channels in
code for the total number of active ports used for
the system. The binary address counts from the counter
channel addresses is strapped into the PORTS IN USE
are the sequential channel addresses that are written
switches.
into the R.A.M. Since the counter is not incremented by
strapped ports, the channel address of the last active
5-272. Write Function.
channel is read into the R.A.M. for each strapped port
assigned to an active channel. Table 5-2 shows a typical
5-273. The major function of the write circuits is to enter
system configuration based on the use of 22 active ports
a 4-bit channel address for each active port into the
associated with nine active channel assignments.
random access memories (R.A.M.) on the card. System
clock signals RIO and RIO- synchronize the circuits on
5-275. The channel addresses from the active channel
the card and are derived from system clock signals
counter are also applied to the maximum-channel-used
MRIO from the OEG card.  The port scan counter is
register, which continually generates a binary count that
clocked by RIO and produces sequential 5-bit binary
is equal to the maximum number of active channels in
counts (S1, S2, S4, S8, and S16) that are the port
the system configuration. The binary count (CHMAXO
addresses to the active port mux, the ports-in-use
through CHMAX3) applied to the display card is, in
comparator, and the active port mux in the channel
effect, a static count that does not change until the
address diagnostics. The counter is incremented until the
system is reconfigured.
end-of-scan signal (DEOS-) from the end-of-scan
register is applied to it. The signal presets the scan
5-276. The R.A.M. accepts channel addresses when a
counter to a count of one.  The end-of-scan register
write enable signal is applied from the write/read control.
generates EOS1 when the ports-in-use comparator has
The R.A.M. can store up to 32 sets of 4-bit words. A
a match between the port address and the 5-bit binary
maximum of 31 sets of 4-bit words (channel addresses)
count from the PORTS IN USE switches. Thus, each
are stored in the R.A.M. when the maximum number of
complete scan (or one data word) has a time duration
active ports (31) are used. The surplus memory stores
that is equal to the RIO duration times the number of
in the R.A.M. are inactive in system configurations that
active ports. For example, 22 RIO clock pulses occur in
use less than 31 active ports. The memory locations that
a 22-bit data word that contains 21 active ports and one
receive the channel addresses are selected by the
overhead bit.
Change 2 5-67

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