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T.O. 31W-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
same. When the data bits are not the same, the data
comparator generates the data error signal (A is not
5-190. DETAILED CIRCUIT DISCUSSION.
equal to B) to the composite card error detector circuit.
5-191. Input-Output Data Buffer Function. 5-192. The
5-186.  The timing activity detector, which is used to
incoming channel data bits (DIXX) are applied to data
force the output data to all zeros when the incoming
receivers U42-1 and U42-8.  The conditioned data
timing to the RCB card is lost, is a retriggerable one-shot
pulses from data receiver No.  1 (U42-1) are applied
multivibrator that is held in conduction by the timing
through inverter U51 to data buffer U41. The incoming
signals from timing receiver No. 1. When the timing
channel timing pulses (TIXX) are applied to timing
signals are missing, the multivibrator's duty cycle expires
receivers U43-1 and U43-8.  The conditioned timing
and the circuit forces the output data buffer to the zero
pulses from timing receiver No. 1 (U43-1) are applied
state and also applies a high-level signal that is applied
through inverters U51-4 and U30-2 to increment write
through OR gate U31 as out-of-tolerance signal OOTXX
address counter U18. The same timing pulses that are
that is applied to the display card.
applied through inverter U30-2 are also used to clock the
data pulses through data buffer U41. The timing pulses
5-187. The out-of-tolerance generator applies a cycling
from timing receiver No. 1 are also applied to AND gates
out-of-tolerance signal OOTXX through OR gate U31
U23-8 and U23-11 to clock the data from data buffer U41
when the functional decoder logic circuit generates an
into U19 or U20 of the data elastic storage register.
out-of-tolerance signal. The out-of-tolerance signal from
the generator is the product of a one-shot multivibrator
5-193. The write address counter (U18) is incremented
that has a duty cycle of approximately 31 seconds.
by the same timing signal that is applied to data buffer
U41. The low level MSB of the 4-bit write address from
5-188. The composite card error detector monitors the
U18-11 is applied through inverter U30-12 to enable
four error signals described above.  When an error
AND gate U23-8 for binary addresses 0 through 7. In
condition is detected, the circuit generates an error
turn, the high-level MSB of the 4-bit address from U18-
signal to the output selector.
11 enables AND gate U23-11 for binary counts 8 through
15. Therefore, the first eight bits of data clocked through
5-189. The output selector applies the error signal from
data buffer U41 are stored in U20 and the next eight bits
the composite error detector to the OEG card, or the
of data are stored in U19. Write address counter U18
selector applies positive stuff (POS) commands to the
continues to cycle until a preset signal from J-K flip-flop
OEG card. The output selector is controlled by word 24
U16-7 in the initialization logic circuits presets its output
signal MW24MXfrom the OEG card.  When signal
to 1010.
MW24NX is applied, the selector samples the composite
card error detector output and transmits signal MPSTXX
5-194.  The gated clocks (MGCXX) from the GC/DM
when a card error is present. When signal MW24NXis
card are applied through inverter U53-6 to AND gate U9.
not present, the selector samples the positive stuff
AND gate
(POS) output from decoder logic No. 1 and transmits
signal MPSTXX when a stuff command is present.
5-46

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