Figure 5-8. Frame Synchronization Function

T.O. 31W2-2GSC24-2

TM 11-5805-688-14-1

NAVELEX 0967-LP-545-3011

6186-85

Figure 5-8. Frame Synchronization Function - Simplified Block Diagram

the multiplexer (paragraph 5-11). An 11-bit stuff code

the stuff code store provides the remaining 12 bits of the

comparator performs a broadside or parallel search for

appropriate one of the three known code possibilities

an exact match between the data flowing through the

under control of the word counter. Each error detected

VLSR and one of three stuff codes contained in the

during the serial comparison is counted by an error

comparator. When one of the three codes is detected

counter whose output is routed to the up/down

without errors, the stuff code comparator sets a parallel

confidence counter. If the number of errors detected

sync latch. This latch, in turn, presets the demultiplexer

during the serial code comparison is two or less, the

word counter and an up/ down confidence counter, and

frame sync latch is set and the frame synchronization

enables a serial error detector. The word counter is

circuits automatically switch to a frame maintenance

preset to 12, since the next received multiplexer word is

mode. If more than two errors are detected, the word

12. The confidence counter is set to a count of 5. Once

counter and parallel sync latch are reset and the frame

parallel sync is established without detected errors in the

acquisition cycle is initiated again.

first 11 bits of the received framing code, the next 12 bits

(11 + 12 = 23 total stuff code bits) of received overhead

5-62. Frame maintenance is accomplished by a serial

data are compared serially by the serial error detector.

23-bit comparison of the received overhead stuffing

enable

comparison,

codes and known codes provided by the stuff.

5-17