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T.O. 31W2-2GSC24-2
TM 11-5805-688-14-1
NAVELEX 0967-LP-545-3011
these inputs are coarse rate converted within the
is applied to the channel card.
The input is
multiplexer, and subsequently processed as rates of the
asynchronous to internal multiplexer timing references.
KR form. The outputs of multiplexers No.P3-1 through
An input counter, clocked by the input timing signal,
3-20 are time division interleaved data streams carrying
enables storage of input data bits in successive cells of
the information from a total of 150 input channels [(5 x
an elastic storage register. The register is designed to
15) + (15 x 5)] = 150.  After being processed by
enable simultaneous data storage and retrieval (write
multiplexers No.  2-1, 2-2, and 1, the combined 150
and read) under control of independently clocked
channels, together with the independent 2.304Mbps
counters. However, write and read of the same storage
channels applied to multiplexer No. 1, appear on a single
cell at the same time is not permitted, so that the input
line that is routed to the communications link.  This
(write) and output (read) counters are nominally
example shows that the AN/GSC-24(V) multiplexer is an
maintained at a predetermined offset.
extremely  flexible  equipment  that  is  capable  of
combining numerous individual data channels of mixed
5-33.  Data stored in the elastic storage register under
rates and forms into a single data stream.
control of the input counter are read from the elastic
storage register under control of an output counter. The
5-30.
PROCESSING OF ASYNCHRONOUS INPUTS
output counter is operated by a gated clock signal
derived from the internal multiplexer reference timing
5-31.
One primary feature of the multiplexer is its
source, and is therefore synchronized with other events
ability to accept and process channel data inputs that are
occurring within the multiplexer common electronics
not  synchronized  with  internal  multiplexer  timing
section.  The result is a single data storage buffer
references or with other channel data inputs.  Such
operated under control of two independently clocked
processing is made possible by the use of a variety of
(asynchronous) counters.  Since the output counter is
channel cards, each designed to handle a given form of
clocked by a multiplexer timing source that is considered
channel data input. The output of each channel card,
to be the reference for all multiplexer set internal timing,
regardless of type, is a digital representation of the data
the result is an asynchronous-to-synchronous conversion
input applied to the card. Furthermore, the output is
of channel data and timing.
synchronized with internal multiplexer timing references
and is subsequently processed as a synchronous signal.
5-34.  The preceding discussion assumes that the
Channel cards thus provide form conversion and rate or
input and output counters addressing the elastic storage
time buffering functions, and present all channel data
register are operated by clock signals of different phases
inputs to the multiplexer common electronics section in a
but having the same rate. However, since clocking of the
digital synchronized form.
counter is performed by the use of independently
generated timing sources, minor differences in clock
5-32.  Figure 5-4 is a simplified block diagram of a
rates are also encountered.
typical channel rate buffering arrangement.
Both
channel card and common electronics elements are
5-35.  Within prescribed limits, the multiplexer is
used in the rate buffering process. A digital input signal,
capable of compensating for input counter-to-output
with
associated
timing,
counter rate
Change 2 5-8

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