INTEGRATED CIRCUIT DESCRIPTIONS-CONT. - TM-11-5805-663-14-130179

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

When the data compliment (pin 16) is low

buffer register made up of ten D-type flip-

the selected non-inverted input is passed

flops. The flip-flops are simultaneously

to the data output (pins 10, 11, 13, and

clocked (pin 1) and reset (pin 23). The

14) if the output enable inputs (pins 7, 8

logic states at the D inputs (pins 2 through

and 9) are high. When the data compliment

11) will appear at the Q outputs (pins 13

is high the selected inverted data input is

through 22) after the high-to-low transition

passed to the data output if the output

of the clock input. The flip-flops will

enable inputs are high. When any one of

show the data at the Q outputs till reset

the output enable inputs goes low, all the

or power recycled without altering their

data outputs go high. When both channel

s t a t e s . The table provided applies to all

selects are low and the output enable input

10 flip-flops.

are all high, the data output follow the

data compliment levels.

5 - 7 7 7 . N8203N, 10-BIT BUFFER REGISTER

INVERTED INPUTS (see figure 139). The

5 - 7 8 0 . N8266B, 2-INPUT, 4-BIT DIGITAL

N8203N is a 10-bit buffer register con-

MULTIPLEXER (see figure 142). The N8266B

sisting of 10 D-type flip-flops. The logic

is a 2-bit binary decoder and multiplexer

state the D inputs (pins 2 through 11) will

which operates as four 2-bit parallel to

invert and appear at the Q outputs (pins 13

serial data converters. Depending on the

through 22) after a high-to-low transition

level of the data select inputs, SO and Sl

of the clock input (pin 1). All 10 flip-flops

(pins 7 and 9), a specific gate is enabled

are reset, Q outputs go low, when the

to pass its corresponding data inputs (pins

reset input (pin 23) goes low regardless

1, 2, 5, 6, 10, 11, 14, and 15) to the

of the clock and D inputs. The data at the

data outputs (pins 3, 4, 12 and 13) as

Q outputs will not alter till the flip-flops

shown in the associated truth table. When

are reset or load with other data. The

both select inputs are high all the data

table provided applies to all 10 flip-flops.

outputs are high. When both data inputs

are tied together the data output will pro-

5 - 7 7 8 . N8235N, 2-INPUT, 4-BIT DIGITAL

vide either the true (non-inverted) or com-

MULTIPLEXER (see figure 140). The

pliment (inverted) of the data input.

N8235N is a 2 bit binary decoder and multi-

plexer which operates as four 2-bit paral-

5 - 7 8 1 . P3205, HIGH SPEED 1 OUT OF 8

lel to serial data converters. Depending

BINARY DECODER (see figure 143). The

on the level of the data select inputs, SO

P3205 is a high speed decoder used in high

and Sl (pins and 9), a specific gate is

speed data routing applications. It gen-

enabled to p

its corresponding data

erates one of eight lines (outputs 00 through

inputs (pins 1, 2 , 5, 6, 10, 11, 14, and

07) that is dependent on the conditions at

15) to the data outputs (pins 3, 4, 12 and

the three enable inputs (E1, E2, and E3)

13) as shown in the associated truth table.

and the select inputs (Al, A2, and A3).

When both select inputs are high all the

The enable inputs are three active low to

data outputs are high. When both data

reduce the need for external gates and in-

inputs are tied together, the data output

will provide either the true (non-inverted)

verters when expanding. The enable inputs

or compliment (inverted) of the data input.

must all be low to enable the decoder.

When the decoder is enabled, it decodes

5 - 7 7 9 . N8264N, 3-INPUT, 4-BIT DIGITAL

the three select input causing the decoded

output (00 through 07) to go low.

MULTIPLEXER (see figure 141). The N8264N

IS triple 2-bit binary decoder which oper-

ates as four 3-bit parallel to serial data

5 - 7 8 2 . P3404, HIGH SPEED 6-BIT LATCH

converters. Depending on the binary

(see figure 144). The P3404 contains six

value of the channel selects, S0 and Sl

high speed latches organized as independent

(pins 16 and 17) a specific gate is en-

4-bit and 2-bit latches. They are designed

abled to pass its corresponding data inputs

for use as memory data registers, address

(pins 1 through 6 and 18 through 23) to the

registers, or other storage elements. Data

output gates (see associated truth table).

applied to the data inputs Dl through D6 is

5-127