TIMING AND CONTROL LOGIC CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

G6 is inverted by inverter I2 which generates

5-728. TIMING AND CONTROL LOGIC

CLOCK2-P (waveform D, figure 111).

CIRCUIT.

CLOCKl-P and CLOCK2-P trigger FF5

through FF12.

5 - 7 2 9 . G e n e r a l . The timing and control

logic circuit is controlled by the Pro-

5 - 7 3 2 . The output of G7, CWST-N (wave-

cessor Core Memory Controller. This

circuit determines whether the Core

form S, figure 111), activates gate G34

generating PRE YRT-P (waveform T, figure

Memory will operate in the clear/write or

111) which is routed to the address register,

read restore mode.

decoding, switching, and control and buf-

fer logic circuit. The output of G34 is in-

5-730. Detail Analysis (See figure 110).

At turn-on, PWR RDY-P enables gate G3.

verted by inverter I5 which causes gate

After the 4 usec delay of delay DLl, G3 is

G23 to go to logic 1 enabling gates G1,

activated which turns off transistor switch

G28, G31, G32, G35, G36, and G37 and

single shot SS2. Gate G30 generates a

Ql, causing GEN RST-N to go high. While

200 nsec positive pulse that activates G31.

GEN RST-N is low (before G3 is activated),

The output of G31, MRT-N (waveform U,

flip-flop FF1 is cleared and gate G20 is

figure 111), is applied to the address regis-

a c t i v a t e d . The 1 output of FFl, BUSY-N

ter, decoding, switching, and control and

(low), presets flip-flops FF5 through FF7

buffer logic circuit to allow current flow

and FF10 and FF11. At this time, BUSY-N

in the core stack, thereby clearing the

also activates gate G2 which generates

c o r e s . The logic 0 output of I5 is inverted

BUSG-N. BUSG-N presets flip-flops FF8,

by inverter I6 which activates G35. The

FF9, and FF12. GEN RST-N also activates

output of G35, RDR-P (waveform V, figure

gate G14 which presets flip-flop FF2,

111), resets the data registers in the sense,

resets flip-flop FF3, and generates CYC

inhibit, and data circuit. G28 generates

E N D - N . If PWR RDY-P goes low (power

a 60 nsec negative pulse that activates

failure has occurred) and BUSY-N is low,

gate G29. G29 generates DIX-P (wave-

the output of G1 goes high causing GEN

form W, figure 111) that clocks the data

RST-N to go low. However, if PWR

into the sense, inhibit, and data circuit

RDY-P goes low during a memory cycle

d a t a r e g i s t e r s . When the output of G21

(BUSY-N high) the output of G3 rernains

returns to logic 1, gate G26 is activated

low until BUSY-N goes low which dis-

because RD ST-N (waveform X, figure 111)

ables G3. Disabling G3 turns on tran-

and CW ST-N are logic 1. Gate G27 gen-

sistor switch Ql which generates GCN

erates a pulse whose leading edge is

RST-N, Another memory cycle cannot be

determined. by T40-P and trailing edge by

started until PWR RDY-P returns to logic 1.

T 1 2 0 - P . The output of G27 is inverted by

invertcr I4 and routed to the Core Memory

5 - 7 3 1 . In the clear/write mode RD INIT-P

sense, inhibit, and data circuit as TINH-P

and RD ONLY-P are logic 0 and FULL CYC-P

(waveform Y, f i g u r e 1 1 1 ) g e n e r a t i n g t h e

and MEM SEL-P are logic 1. Under these

inhibit current through the cores where

c o n d i t i o n s , WT INIT-P (waveform A, figure

a zero is to be stored. TINH-P is also

111) activates gate G7 which sets

inverted by invcrter I3 and pulse shaper

F F l . The output of G7 activates gate G11

C23, R35, and R36 generates a 33 nsec

which generates AIX-P (waveform B, figure

positive pulse on the trailing edge of

111). The output of G7 also clears flip-

TINH-P which activates gate G13. The

flop FF4. A M - P c l o c k s t h e a d d r e s s r e g i s -

output of G13 activates G14 which gener-

ter decoding, switching, and control and

ates CYC END-N. CYC END-N is applied

buffer logic circuit.

Disabling G8

to the Core Memory a d d r e s s r e g i s t e r , d e -

activates gate G5 which enables the ossscil-

coding, switching, and control a n d b u f f e r

lator consisting of gates G5 and G6 and the

logic circuit to set the cycle busy flip-

shifter. T h e o u t p u t o f G 5 i s i n v e r t e d

phase

by inverter I1 which generates CLOCK1-P

(waveform C, figure 111). The output of

5-116