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Page Title: CORE MEMORY DETAIL LOGIC DIAGRAM DESCRIPTION
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T.O. 31S5-4-306-1
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
inverted by I10 which ensures FF3 is
the information on the INFIBUS data lines
is displayed by the address LEDS.
c l e a r e d .  The output of G13 also activates
G14 which activates G16. The output of
5-725. If RITE-N is high (another func-
G16 resets FF8.  The output of FF8 is in-
tion reading from Program Maintenance
verted by I11 causing the ATTN LED
Panel), the output of I2 disables G6 and is
t o g o o u t .  RElS-N activates G25
coupled through I3 enabling G2. When
which ensures FF8 is cleared. With FF6
the Program Maintenance Panel recognizes
and FF8 cleared, G31 is enabled. When
its address on the INFIBUS address lines
DONE-N returns to high, G27 is disabled.
(slave mode), SARP-P goes high activating
This high output of G27 activates G31
G2. The output of G2 sets FFl. The out-
w h i c h c l e a r s F F 1 2 .  The 0 output of FF12
put of FF1 activates G3 causing DOUT-P
IS inverted by I13 which disables G32.
to go high.  If ABOl-N is low, AOIA-P is
The output of I13, STRF-N, is also coupled
high, and DOUT-P strobes the information
through DR2 causing STRB-N to return to
stored in the data shift register of the
high.  When STRB-N goes high, the output
Program Maintenance Panel address/data
of I4 resets FF2, ensures FF1 is cleared,
switch identification, multiplexers, and
and SS1 is reset.
LED circuit to the INFIBUS data lines. If
ABOl-N is high, AOIA-P is low and DOUT-P
strobes the information stored in the ad-
5 - 7 2 3 .  If DONE-N is not generated within
dress shift register of the Program Mainte-
2 usec after STRB-N goes low, the Bus
nance Panel address/data switch identifi-
Controller generates QUIT-N. QUIT-N is
cation, multiplexers and LED circuit to the
inverted by I16 and I17. The output of I17
INFIBUS data lines.  The output of FFl also
d i s a b l e s G 3 7 .  The output of I16 activates
G38 which sets FF14. The output of FF14
activates G4 which triggers SSl. The
trailing edge of the 100 nsec pulse out of
clears FF12 causing STRB-N to go high and
FFl, FF2, and SS1 are reset, is explained
SSl presets FF2 which activates G.5. 50
nsec later G5 is disabled by I5 and DLl.
previously.
This low output of DL2 resets FFl which
causes DOW-P to return to high by dis-
5 - 7 2 4 .  If RITE-N is low (another function
abling G3.  This SO nsec pulse out of G5
writing into the Program Maintenance Panel)
is coupled through DRl causing DONE-N
the output of I2 enables G6. When the
to go low for 50 nsec. At the end of the
Program Maintenance Panel recognizes its
DONE-N pulse the module addressing the
address on the INFIBUS address lines
Program Maintenance Panel causes STRB-N
(slave, mode), SARP-P goes high activating
to go high and removes the Program Mainte-
G 6 .  The output of I2, is also coupled
nance Panel address from the infibus ad-
through I3 which disables G2. The output
Cress lines which causes SARP-P to go low.
of G6 activates G4 and G7 because OLTS-P
When SARP-P goes low G2 is disabled and
i s l o w .  The output of G4 triggers SS1
STRB-N via I4 clears FF1.
which  disables  gate  G8  for  100  nsec  and
presets FF2.  When the output of SS1 re-
5-726. CORE MEMORY DETAIL LOGIC
turns to high, G8 is activated causing
DIAGRAM DESCRIPTION.
SWRG-P to go high.  I f A B O l - N i s l o w ,
G10 is enabled inverter I7 and G9 is
disabled
by  inverter  I8  SWRG-P  activates
G10 causing DSCB-N to go low and the
information
on the INFIBUS data lines is
displayed by the d a t a L E D S .  If AB01-N
is high, G9 is e n a b l e d  b y  I 7  a n d
G10 is disabled by I7.  SWRG-P now acti-
vates causing ASCB-N to go low and

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