PROGRAM MAINTENANCE PANEL SWITCH FLIP-FLOPS AND SINGLE ACTION DISGRIMINATOR CIRCUIT

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

is strobed to the INFIBUS by DOUT-P when

identification, multiplexers, and LED cir-

RNDB-P and HTDB-P are low and VADB-P is

cuit to disable the address and data 00

high. Operation is similar to when the ad-

through 15 switches.

dress shift register or data shift register

information is strobed to the INFIBUS,

5-679. If the halt switch (S59) is touched,

except the output of G16 is held high by

the output of inverter I2 goes high. The

VADB-P via G15, forcing all outputs of

output of I2 is coupled through G-3 to the

data multiplexers U6, U16, U26, and U36

switch flip-flops and through G2, G4, G5,

low. The high level of VADB-P also forces

G6, G7, and G8, causing 7ACT-P to go

the outputs of G12 through G10 low, over-

high. The associated switch flip-flop is

riding the low outputs of data multiplexers

set and ANRW-N is generated, as explained

U6, U16, U26, and U36. When DOUT-Pgoes

previously.

high the Program Maintenance Panel ad-

dress is strobed to the INFIBUS.

5 - 6 8 0 . If the step switch (S61) is touched.

the step LED (CR64) lights and the output

5-676. PROGRAM MAINTENANCE PANEL

of inverter I3 goes high. The output of I3

SWITCH FLIP-FLOPS AND SINGLE

is coupled through Gl and G3 to the switch

ACTION DISGRIMINATOR CIRCUIT.

flip-flops and through G4, G5, G6, G7

and G8 causing 7ACT-P to go high. Two

5 - 6 7 7 . General. The Program Maintenance

switch flip-flops are set and ANRW-N is

Panel switch flip-flops and single action

generated, as explained previously.

discriminator circuit detects the closure of

either the run, halt, step, address read,

5 - 6 8 1 . If the address read switch (S38) is

address write, resister read, or resister

touched, the address read LED (CR38)

write switches and clock this information

lights and the output of inverter I4 goes

into the switch registers. If two switches

high. The output of I4 is routed to the

are touched at the same time, information

switch flip-flops and coupled through G5,

is not clocked into the switch flip-flops.

G6, G7 and G8, causing 7/ACT-P to go

These circuits also disable the address and

high. The associated switch flip-flop is

set, as explained previously. The output

data 00 through 15 switches.

of I4 also activates gate G16, which dis-

5-678. Detail Analysis (see figure 104).

ables G19, preventing ARNW-N from being

Initially, MREU-N activates gate G17

generated.

which resets flip-flop FF2. If run switch

(S58) is touched, the output of inverter I1

5 - 6 8 2 . If the address write switch (S20)

goes high. The output of I1 is coupled

is touched, the address write LED (CR20)

through gate G1 to the switch flip-flops

lights and the output of inverter I5 goes

(FFl shown) and through gates G2, G4, G5,

high. The output of I5 is routed to the

G6, G7, and G8 causing 7ACT-P to go high

switch flip-flops and coupled through G6,

which enables gate G15. 1.9 msec after

G7 and G8, causing 7ACT-P to go high.

7ACT-P goes high, OASC-P goes high for

The associated switch flip-flop is set, as

3 . 4 usec, activating G15 which sets FF2

explained previously. The output of I5

when OACS-P goes low. Setting FF2

also activates G16 which disables G19,

causes single shot SSl to generate a 3.4

preventing ANRW-N from being generated.

usec pulse that sets FFl. 7ACT-P also

activates gate G18 which enables gate G19.

5 - 6 8 3 . If the reqister read switch (S19) is

OACS-P activates Gl9 for 3.4 uscc, 1.9

touched, the output of inverter I6 goes

msec after 7ACT-P goes high. The delayed

high. The output of I6 is routed to the

3.4 usec pulse, ANRW-N, is routed to the

switch flip-flops and coupled through G7

Program Maintenance Panel state genera-

The

and G8, causing 7ACT-P to go high.

associated switch flip-flop is set and

tion and micro operations circuit. When

ANRW-N is generated, as explained

FF2 is set, PBAS-P is high and is routed to

the Program Maintenance Panel switch

previously.

5-104