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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
word onto the INFIBUS. This causes the
the I/O Controller INFIBUS access logic
circuit.
Mag Tape Controller data output and con-
trol register circuit to generate BONA-P
5-611. Detail Analysis (see figure 91).
which enables gate G6. When the transfer
of the data word by the Block Transfer
The INFIBUS clock signal, CLKA-N (wave-
Adapter is completed, the Mag Tape Con-
form A, figure 92), is inverted by inverter
I3 and applied to the trigger inputs of flip-
troller address receiver and recognition
flops FFl and FF2. For this discussion
circuit generates BDNA-P.
assume FFl and FF2 are initially in the
reset state. With FF1 and FF2 reset, gates
5-606. BDNA-P activates G6 and the out-
Gl and G2 are disabled. The output of G2
put of G6 activates G7 which resets FF3.
prevents FF2 from being set. The first
This causes G12 to be disabled which re-
positive going edge out of I3 sets FF1.  The
moves BTAl-N. Afterwards, BDNA-P is
0 output of FF1 (waveform B, figure 92)
removed by the Mag Tape Controller INFI-
BUS access circuit which disables G6.
activates G2 and the 1 output of FFl enables
Gl. The second positive edge out of I3
This causes G7 to be disabled and the low-
to-high transition output of G7 triggers and
clears FFl and sets FF2. The 0 output of
sets FF2. The cycle for reading the next
FF2 now activates G2 and the 1 output of
word from the Formatter is repeated as dis-
FF2 enables Gl. The third positive going
cussed.
edge out of I3 sets FFl (FF2 remains set
because G2 activated). With FF1 and FF2
set, G1 is activated. After the inherent
5-607. If during the read operation cycle
the Formatter is not ready to transfer data,
gate delay of Gl, the output of Gl goes
it generates RDNR-P which disables gate
low which resets FF1 and FF2. Resetting
FFl and FF2 causes the entire sequence to
G8. G8 generates RDNR-N which activates
repeat itself. The 1 output of FF2, Q2-P
gate G9 and G9 activates G10 and G14.
G10 resets FF2 and G14 generates EROR-N.
(waveform C, figure 92), is inverted by in-
The read operation cycle is inhibited and
verters I2. and I1 which generate Ql-N and
the Mag Tape Controller INFIBUS access
Q3-N, respectively.
circuit initiates an interrupt to indicate a
5 - 6 1 2 . I/O CONTROLLER ADDRESS RECOG-
read timing error.
NITION, DONE, AND RESET CIRCUIT.
5-608. If the Block Transfer Adapter does
5-613. General.  The I/O Controller address
not slave the Mag Tape Controller to pre-
recognition, done, and reset circuit detects
sent the data word on to the INFIBUS before
when the I/O Controller is being addressed
the next data word is presented by the
(slaved) using address bits AB04-N through
Formatter, an overrun condition occurs.
AB15-N and decodes address bits ABOO-N
The previous data word is destroyed. FF3
through AB03-N to select either the Rapid
is not reset by G7, as discussed, and
Memory Reload (RMR), Register Sender
RDSP-P triggers and sets FF4 which gener-
Junctor (RSJ), or Call Combiner Logic (CCL)
ates RTER-N. RTER-N activates G9 which
functions.  The i/O Controller address
activates GlO and G14. G10 resets FF2
recognition, done, and reset circuit strobes
and G14 generates EROR-N. The read
the data command word through the I/O
operation cycle is inhibited and the Mag
Controller data circuits. The I/O Controller
Tape Controller INFIBUS access circuit
address recognition, done, and reset cir-
initiates an interrupt to indicate an over-
cuit also generates the DONE-N signal that
run condition,
is routed to INFIBUS and generates reset
signals that are routed to the RMR, RSJ, and
5-609. I/O CONTROLLER CLOCK CIRCUIT.
CCL functions and to the I/O Controller
INFIBUS access logic circuits and data cir-
The I/O Controller clock
5-610. General.
cuits.
circuit divides the INFIBUS clock signal,
5-614.  Detail Analysis (see figure 93).
CLKA-N, by three and supplies timing pulses
When the master reset pulse, MRES-N, is
to the I/O Controller interface circuit and

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