MAG TAPE CONTROLLER READ/ WRITE CONTROL STATUS CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

and U80

triggers and clears FFl which removes

which couples DOOA-N through

D15A-N

to the INFIBUS data lines.

WBAS-P and WBAR-N, and G12 is disabled

Gate G4 acti-

and G4 is activated.

MAG TAPE CONTROLLER READ/

5-595.

vates G5 which activates I1 which

WRITE CONTROL STATUS CIRCUIT.

generates WDGA-N to the Formatter.

5 - 5 9 6 . G e n e r a l . The Mag Tape Controller

The Formatter accepts the data word

read/write `control status circuit controls

and removes WDDC-N which disables

the transferring of data to or from the

Gl. G4 is disabled and WDGA-N is

Formatter. It controls writing or reading

removed.

Also, the high to low

operations of data with the Formatter and

transition output of Gl sets single-

provides error indications for timing errors

shot SSl which activates G2.

and overrun conditions.

5 - 5 9 7 . Detail Analysis (see figure 90).

G2 presets FFl which generates

5-601.

When the master reset pulse is generated

WBAS-P and WBAR-N and the cycle

on the INFIBUS or when the MAG TAPE CON-

previously discussed is repeated

TROLLER status register is written, the

for the next data word.

Mag Tape Controller data output and control

5-602.

Read.

With a read operation

GRSC-P. GRSA-N resets flip-flop FF4, and

control word stored in the data

activates gate G7 which resets flip-flop

output and control registed circuit,

FF3. GRSC-P activates gate G2 which pre-

WRCO-P, CROA-P, and CROS-P are

sets flip-flop FF1. FF1 then generates

WRCO-P and CROA-P

generated.

WBAS-P and WBAR-N. WBAS-P enables

activates gate G3 which presets FF2.

half of gate G12 and is also routed to the

CROS-P enables gate G11, half of

Mag Tape Controller data output and con-

gate G12, half of gate G14, and the

trol register circuit. WBAR-N disables

set input of FF2. The 1 output of

gate G4 and is also routed to the Mag Tape

FF2 is inverted by inverter I2

Controller address receiver and

which disables G11.

recognition circuit.

5-598. With operation control word

stored in the Mag Tape Controller data out-

5 - 6 0 3 . The Formatter presents a data word

put and control register circuit, CRIS-P is

to the Mag Tape Controller which causes

generated which enables G4 and activates

the Mag Tape Controller data input and

G 1 2 . G12 generates PDSA-N which is

selector circuit to generate RDSP-P and

routed to the Mag Tape Controller data

RDST-N when IDSB-N is generated.

input and selector circuit and Mag Tape

RDSP-P triggers FF4 and activates gate

Controller INFIBUS access circuit.

G10 which resets FF2. RDST-N is

PDSA-N is also coupled through driver

inverted by inverter I4 which enables

DR1 which generates BTAl-N.

G11. With FF2 reset, 12 activates G11

5-599.

When the Formatter is ready to

and G11 generates ISB-N which is

accept the data word, it generates

routed to the Formatter to indicate a

WDDC-N which activates gate G1. G1

successful transfer.

enables G4.

The output of gate G13 is

5-604. The Mag Tape Controller data in-

always low which keeps half of gate

put and selector circult removes RDSP-P,

G14 disabled. Also, i n v e r t e r I 5

which disables G10, and RDST-N, which

inverts the output of G13 and enables

triggers sets FF3. The 1 output of FF3

G4.

enables the set input of FF4 and also acti-

5-600. To present a data word to the

vates G12, which generates BTAl-N. With

Formatter, the Block Transfer Adapt-

RDST-K removed, I4 disables G11 which

removes ISB-N.

er slaves the Mag Tape Controller

which causes the Mag Tape Controller

data output and control register

c i r c u i t t o g e n e r a t e W D R B - N , WDRB-N

5-87