AUTOLOAD AlA3A9 CONTROL CIRCUIT

T.O. 31S5-4-308-l

TM 11-5505-663-14-13

NAVELEX 0967-464-0010

high and RLDR-N low, a direct data

PO-N through P3-N, which represents the

transfer INFIBUS access is requested by

page number, are routed to bus driver receivers

the Autoload INFIBUS access logic circuit

U44 (G3 shown typical). RDST-P is gen-

and, when gained, 0006 16 is strobed to

erated which strobes the page number to the

the INFIBUS address lines and the ad-

INFIBUS data lines, DBOO-N through DB03-N.

dress FBOO is strobed to the INFIBUS data

l i n e s . When the direct data transfer is

5-344. AUTOLOAD AlA3A9 CONTROL

complete, DONE-N goes low for 50 nsec.

CIRCUIT.

DONE-N is inverted by inverter I8. The

output of I8, BDNA-P, causes the Auto-

5 - 3 4 5 . General. The Autoload control

load INFIBUS access circuit to cause

circuit detects the autoload signal and

ACLK-N to go low for 50 nsec. ACLK-N

causes the Autoload INFIBUS access circuit

activates G5 which resets FF3. The

to generate a direct data transfer. When

output of I8 is also inverted by inverter

the direct data transfer is complete, the

I7 which presets FF6. Presetting FF6

Autoload control circuit then causes the

insures FF2 will not be set until after

Autoload INFIBUS access circuit to

generate a level 1 interrupt request for

another MRES-N pulse is received. Re-

data transfer. When the Autoload

settling FF3 sets FF4 which causes the

address recognition and ROM select cir-

Autoload INFIBUS access circuit to gen-

cuit recognizes the Autoload address,

erate a level 1 interrupt data transfer

the Autoload control circuit clocks and

request. When the level 1 interrupt data

controls the Autoload ROM and data select

transfer is complete BOLK-N goes low

circuit.

for 50 nsec activating G6 which resets

FF4.

5 - 3 4 6 . Detail Analysis (see figure 34).

5 - 3 4 8 . If the Autoload control circuit

Initially, the Autoload control circuit

does not receive a DONE-N pulse within

receives a master reset pulse, MRES-N

2 usec after INFIBUS access is gained,

from the INFIBUS. MRES-N is inverted

ABRT-N goes low, activating G5 and G6

by inserter I2 and the output of I2 is

which resets FF3 or FF4 depending on

inverted by inverter I3. The output of I3

resets flip-flops FF2 and FF6, resets the

which one was set.

S-bit shift register U65, and activates

gates G5 and G6. The output of G5 re-

5-349. The 25 MHz clock pulses,

sets flip-flop FF3 and the output of G6

CLKA-N (waveform A, figure 35), are

resets flip-flop FF4. The output of I2 is

coupled through inverter I10 and divided

also inverted by inverter I1 which resets

by two by flip-flop FFl0. Gate G8 is

flip-flop FF1 and single shots SSl and

enabled by the 5 volts and gate G10 is

SS2. Also, AMAS-P is normally low hold-

disabled by the logic 0 out of inverter I9.

ing flip-flops FF5 and FF7 reset.

The 12.5 MHz pulses out of FF10 acti-

vates G8 which activates gate G9 at a

5 - 3 4 7 . When an Autoload pulse, ATLD-N,

12.5 MHz cate. If the J4 jumper was

is generated by the Program Maintenance

installed, G10 would be activated and G8

Pans: or Bus Controller, it is coupled

would be disabled. The 12.5 MHz out-

through driver DRl which activates gate

put of FF 10 would be divided by two by

G l . The trailing edge of the Gl output

flip-flop FF11. This 6.2.5 MHz output

sets FF1 which will remain set until the

of FF11 would activate G10 which would

next MRES-N pulse is received. The

activate G9 at a 6.25 MHz rate.

output of FF1 triggers SSl. The 0 output

5 - 3 5 0 . The 12.5 MHz output of G9

of SSl activates gate G4 which resets

flip-flops FF8 and FF9. 140 msec late:

waveform B, figure 35) enables gates

the trailing edge of the 1 output of SSl

G11 and G12 at a 12.5 MHz rate and is

triggers FF2 which disables Gl. The 0

divided by two by flip-flop FF12. The 1

output of FF2 sets FF3 and RLDS-P and

output of FF12 enables G11 at a 6.25

RLDR-N are generated. With RLDS-P

MHz rate and the 0 output of FF12 acti-

5-49