CORE MEMORY CONTROLLER AlA3A8 DATA TRANSFER CIRCUIT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

MODE-P activates G2 and associated

data drivers. The Core Memory Controller

gates). PAGE MODE-N enables gate Gl

command and page select circuit generates

and associated address selector/driver

the PLI-P parity bit, BYTE MODE-P and

gates to couple PO-P, Pl-N, IJ17-P and

BYTE MODE-N. BYTE MODE-N enables

IH06-P (page number) to the Core Memory

gate G4 and associated data selector/

input address lines, AI12-P through AI15-

drivers to couple DBOO-P through DB07-P

P, respectively.

and PLO-P to the Core Memory input data

lines, DI09-P through DI17-P, respectively.

Also, DRl and associated data drivers

5-335.

CORE MEMORY CONTROLLER

AlA3A8 DATA TRANSFER CIRCUIT.

couple DBOO-P through DB07-P and PLO-P

to the Core Memory input data lines, DI00-P

through DI08-P, respectively. The data the

5-336. General. The Core Memory Control-

Core Memory will accept, DIOO-P through

ler data transfer circuit receives and trans-

mits data to and from the INFIBUS data lines

DI08-P (zone 1) or DI09-P through DI17-P

(zone 2), depends on the commands from

and Core Memory under control of the Core

Memory `Controller command and page select

the Core Memory Controller command and

circuit.

page select circuit to the Core Memory.

5-337. Detail Analysis (see figure 33).

5-340. Data receivers (I1 shown) receive

The data bus driver/receivers (inverters I2

data from the Core Memory that is to be

and I3) receive the data word, DBOO-N

placed on the INFIBUS data lines. Inverter

through DB15-N, from the INFIBUS and gen-

I1 and associated data receivers invert

erates DBOO-P through DBl5-P. DBOO-P

D000-P through D007-P and D009-P through

through DB15-P are routed to the Core Mem-

D016-P, generating D000-N through D070-N

ory Controller command and page select cir-

and D090-N through D160-N, respectively.

cuits, and also to the data selector/drivers

5-341. When reading a 16-bit word out of

and the data drivers. The data selector/

the Core Memory, the Core Memory Con-

drivers and data drivers couple the data

troller command and page select circuit

DBOO-P through DB15-P, and parity bits,

generates DAEN-P and DBEN-P. DBEN-P

PHI-P and PLO-P, to the Core Memory input

activates gate G2 and associated date bus

data lines, DI08-P through DI17-P.

driver/receivers coupling D000-N through

DO70-N to the INFIBUS data lines, DBOO-N

5-338. When data is to be transferred into

through DB07-N.

the Core Memory (write) as a 16-bit word,

gate G1 and associated data bus driver/

the Core Memory Controller command and

receivers coupling D090-N through D160-N

page select circuit generates both parity bits,

to the INFIBUS data lines, DB08-N through

PHI-P and PLO-P. Also, BYTE MODE-P is

DB15-N-

low and BYTE MODE-N is high. The low

BYTE MODE-P enables gate G3 and associ-

5-342. When reading data out of the Core

ated data selector/drivers to couple DB08-P

Memory in 8-bit bytes, the Core Memory

through DBl5-P and PHI-P to the Core Mem-

Controller command and page select circuit

ory input data lines, DI09 -P through DIl7-P,

generaces DBEN-P for a zone 1 read or

respectively. Driver DRl and associated

DCEN-P for a zone 2 read (determined by

data drivers couple DBOO-P through DB07-P

the address). DBEN-P, zone 1, activates

and PLO-P to the Core Memory input data

G2 and associated data bus driver/receivers

lines, DIOO-P through CIO8-P, respectively.

coupling D000-N through DO70-N to the

INFIBUS data lines, DB00-N through DB07-N.

5-339. When the data is to be transferred

DCEN-P, zone 2, activates gate G6 and as-

into the Core Memory (write) as an 8-bit

sociated data bus drivers c o u p l i n g D 0 9 0 - N

byte, the data on the INFIBUS is right byte

through D160-N to the INFIBUS data lines,

justified. That is, only DBOO-N through

DB00-N through DB07-N.

DB07-N will be received from the INFIBUS

5-343.

and only DBOO-P through DB07-P will be

presented to the data selector/drivers and

5-48