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Page Title: CORE MEMORY CONTROLLER AlA3A8 COMMAND AND PAGE SELECT CIRCUIT-CONT.
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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
(waveform B, figure 30), which is inverted
5-304.  Detail Analysis (see figure 29).
by I3.  The output of I3 triggers single-shot
The Core Memory full cycle input, FULL
SSl and enables gate G21. 40 nsec later,
CYC-P, and the memory select input, MEM
SSl resets and its output triggers command
SEL-F, are always generated (tied to 5 volts)
register U35 and FF2.
which causes the Core Memory to always be
selected and perform only full cycle opera-
5-308. At this time, command register U35
t i o n s . The Core Memory read only input,
is loaded with the high Dl input and the Ql
RD ONLY-P, is always disabled (tied to
output enables gate G5 and activates G3.
ground) which prevents the Core Memory
The output of G3 is inverted by inverter I7
from performing a read only operation.
which activates gate G4 triggering read/
5-305. Initially, the Core Memory Control-
write register U50.  The Q1 output of com-
ler is cleared by master reset pulse, MRES-N.
is low which activates
mand register U05
MRES-N is inverted by inverter I19 and the
gate G23 and its output enables gate G22.
output of I19 is inverted by inverter I20.
The Q3 output of command register U35 is
The low output of I20 clears the page reg-
low and is inverted by inverter I2 and its
ister U57 an-l flip-flops FF4 and FF5. When
output, BYTE MODE-N, is high which acti-
the Core Memory is not being accessed,
vates gates G13 and G16. The output of G13
the memory available input, MEM AVAIL-P,
enables gate G14 and the output of G16
from Core Memory is high, enabling gate G3
enables G17. Command register U35 Q3
and single shot SS2. The strobe input,
output is high which is inverted by I4 and
STRB-N, is normally high and inverted by
the output of I4 BYTE MODE-P is low. With
inverter I3 which resets the command reg-
BYTE MODE-N high and BYTE MODE-P low,
ister U35 and the read/write register U50.
the Core Memory Controller data transfer
The output of I3 also presets flip-flop FF2
circuit selects the full 16-bit data word to
and disables gate G21. The Ql output of
be transferred to the Core Memory.
the read/write register U50 is low which
resets flip-flop FFl and the Q3 output is low
5-309. With RITE-IN low, read/write reg-
which resets flip-flop FF3. The 0 output of
ister U50 is loaded with a high D3 and D4
FF2 disables gates G10 and G11. The out-
input.  The Q3 output of read/write register
put of gate Gl is high for all addresses ex-
U50 is high which enables FF3 to be set.
cept addresses between E000 and FFFF and
The Q3 output of read/write register U50 is
the high output is routed to the Dl input of
low which activates SS2 and the Q4 output
the command register U35.
is high which activates G4 until read/write
register U50 is cleared.
5-306. If a master function is writing a 16-
bit data word into the Core Memory, it
5 - 3 1 0 . SS2 remains set for 250 nsec. The
places a Core Memory address on the INFIBUS
1 output of SS2 is high which activates G14
address lines, data on the INFIBUS data
and G17. The outputs of G14 and G17 are
lines, and generates RITE-N for a write oper-
coupled through drivers DRl and DR2, re-
ation. The INFIBUS address is modified and
transferred to the Core Memory address input
spectively, generating ZWl-P (waveform C,
lines by the Core Memory Controller address
figure 30) and ZW2-P (waveform D, figure
30).  ZWl-P (right byte) and ZW2-P (left
transfer circuit. The data is transferred to
byte) commands the Core Memory to accept
the Core Memroy data input lines by the Core
Memory Controller data transfer circuit.
both zones (9-bits/zone). The 0 output of
SS2 is low which is inverted by inverter I13.
5-307.  RITE-N (waveform A, figure 3(j) is
The high output of I13 is coupled through
inverted by inverter I5 and the high output
driver DR3 which generates WT INIT-P
is routed to the D3 input of the read/write
(waveform E, figure 30). WT INIT-P com-
register U50. Inverter a also inverts the
mands the Core Memory to initiate a write
high output of IS, placing a low on the D1
cycle for the incoming word. After a delay,
input of read/write register U50. The master
MEM AVAIL-P (waveform F, figure 30) goes
function then generates its strobe, STRB-N
low indicating the Core Memory is busy.
5-43

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