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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
RBFR-N from the CPU control circuit is high
activate gate G8, BAl0-P through BA12 -P
which enables gates G10, G13, and G15.
activate gate G6, and BA13-P through BAl5-P
When a register is addressed to have data
activate gate G4. CPU1-P and CPUO-P
written into it, the CPU INFIBUS access
from the Bus Controller are always low and
circuit generates WRIT-P which enables gates
when BAO6-P and BAO5-P are low, the output
G10, G24, and G25. Inverter 16 inverts
of gates G12 and G14 are high. BAO7-P is
WRIT-P which disables gates G1 and G23.
also low and the output of inverter I1 is high.
When Address recognition occurs, the 1 output
of FF3 activates G10, G13, and G18 and
5-255. The high outputs of G4, G6, G8, I1,
enables G15. The output of Gl0 activates
G12 and G14 are coupled through driver DR1
gate G3 which generates RDCK-P. RDCK-P
which generates SARC-P. SARC-P signifies
causes the CPU receive register circuit to
the address is valid and the set input of FF3
read data from the INFIBUS data lines. The
is enabled. The function slaving the CPU
output of G13 activates G24 and G25 and the
then generates STRB-N which is inverted by
CPU microcode register circuit receives
inverter I3. The output of I3 is coupled
only UB02-P (output of G23). UB02-P mod-
through driver DR3. At the same time,
ifies the microcode word which allows the
STRR-P from the CPU INFIBUS access cir-
data to be written into the selected register
cuit is generated which disables the reset
of the CPU register file circuit. The output
input of FF3. Inverter 14 inverts the output
of G 18 activates G20 which generates
of DR3 and generates STRC-N which triggers
CKEN-P to the CPU central timing control
and sets FF3. Setting FF3 signifies that
circuit which initiates the cycle of writing
address recognition has occurred.
data into the selected register. The CPU
central timing control circuit then generates
5 - 2 5 6 . When the control register of the
CMEN-N which clears FF4 and disables
CPU is addressed, the CPU emulation in-
struction register circuit generates BADF-P
G10 and G18 causing CKEN-P and RDCK-P
which enables gate G16 when address recog-
to be removed. The CPU central timing
nition occurs the 1 output of FF3 activates G16  control circuit generates Z150-N 150 nsec
and G18. The output of G16 generates
later which activates gate G22. The output
WARC-P which clocks the control register
of G22 activates Gl5 and the output of G15
in the CPU control circuit. The output of
activates G7 which triggers and sets FF2.
The 1 output of FF2 activates G9 and the
G18 activates G20 which generates CKEN-P
to the CPU central timing control circuit.
output of G9 is coupled through DR2 which
Inverter I5 inverts WARC-P which activates
generates DONE-N. The output of DLl
gate G7. The 1 output of FF2 activates
activates G11, 50 nsec later which disables
G9 and resets FF2. Disabling G9 removes
G9 and its output is coupled through driver
DR2 which generates DONE-N. The output
DONE-N and, as explained previously, FF3
of G7 triggers and sets FF2. The CPU central
is cleared.
timing control circuit now generates CMEN-N
which clears FF4 and disables G18 which
5-258. When a register is addressed to
causes CKEN-P to be removed. Delay DLl
have its data read (placed on INFIBUS), the
delays the 1 output of FF2 for 50 nsec and
operation is similar to writing data into the
then the output of DLl activates G11. The
register except, WRIT=-? is not generated by
output of G11 disables G9 (DONE-N returns
the CPU INFIBUS access circuit. G10, G24
to high) and resets FF2. The function ad-
and G25 are disabled and the output of I6
enables Gl and G23. When G13 is activated,
dressing the CPU senses the removal of
Gl and G23 are activated. The output of G1
DONE-N and removes STRB-N causing the
activates gate G2 which generates WOLN-p
CPU INFIBUS access circuit to remove
to the CPU receive register circuit which
STRR-P which resets FF3.
enables the data to be placed on the
INFIBUS data lines. With G23 activated,
5-257. When the CPU is in the halt mode,
the CPU microcode register circuit receives
the CPU registers can be addressed.
5-37

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