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Page Title:
CPU ADDRESS RECOGNITION CIRCUIT |
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 T.O. 31S5-4-308-1
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
5-245. When M18T-P and M19T-P are both
U11 and L2 field modification multiplexer
high, G2 is activated which enables X field
U14. G4 disables the data table ROM's 11
modification multiplexer U15. Also, M18T-P
and 12 (U12 and U13).
and M19T-P cause X field modification
multiplexer U15 to couple BAOl-P through
CIRCUIT.
BAO4-P to the FO through F3 outputs.
UB20-P through UB23-P assume the logic
levels of data BAOl-P through BAO4-P and
5-251. General. The CPU address recog-
are routed to the CPU microcode register
nition circuit recognizes the CPU address
circuit to modify the X field of the microcode
and enables read or write operations with
word.
internal registers of the CPU. The CPU
address register circuit senses the address
5-246. When the CPU control register is
on the INFIBUS and enables the CPU receive
addressed, the CPU address register
register circuit to place data on the INFIBUS
circuit generates BAOl-P through BAO4-P
or read data from the INFIBUS.
which activates gate G3. The output of G3,
BADF-P, is routed to the CPU address recog-
5-252. The CPU is assigned address FFxy l6
nition circuit which allows the control
where x is 0 or 1 and y is an even number
register to be selected.
from 016 to E16 which allows selecting 1 of
the 12 addressable registers in the CPU
5-247. Table ROM address multiplexers U2
register file circuit or the control register
and U4 select either EOOS-P through E03S-P,
in the CPU control register circuit. The
E04S-P through E07S-P, E08S-P through
registers addresses are as follows:
E11S-P, or E12S-P through E15S-P, as deter-
mined by the levels of M08S-P and MOSS-P.
ADDRESS
REGISTER
The outputs (1Y and 2Y) of table ROM ad-
FF00 16
Register 1
(RO)
dress multiplexer-s U2 and U4 are used to
Register 2
(Rl)
FF04 16
address the data table ROM's 11 and 12
Register 3
(R2)
(U12 and U13), and are also inputs to the
Register 4
(R3)
FF08 16
M field modification multiplexer U11.
Register 5
(R4)
Register 6
(R5)
16
M06S-P, M07S-P, M10S-P, and M11S-P
FFOA16
from the CPU microcode register circuit are
Register
7 (R6)
FFOC16
also used to address the data table ROM's
Register
8 (R7)
FF10 16
11 and 12 (U12 and U13).
Register
9 (R8)
Register
1 0 (R9)
16
FF14 16
5-248. The Ll field modification multiplex-
Register 11 (R10)
er U21 selects either TOOR-N and T15R-N
Register 12 (11)
FF16 16
from the CPU receive register circuit,
FFlE 16;
*Control Register (R15)
A16R-N and A17R-N from the CPU address
Located in CPU control
*Note:
register circuit, or OVFS-P, CRYS-P and
register circuit.
ONAR-N from the CPU control circuit.
CPU1-P and CPUO-P from the Bus Control-
5-253. Detail Analysis (see figure 24).
ler A1A3AS are always low and are inputs to
When master reset, MRES-N, is generated
L2 field modification multiplexer U14.
o n t h e INFIBUS, the CPU control circuit
ILlR-N and ILOR-N from the Bus Controller
generates MRST-P w h i c h activates gate G11.
represent the interrupt level being cycled
The output of G11 resets flip-flop FF2 and
by the Bus Controller and CPU. ILOR-N
c l e a r s f l i p - f l o p F F 1 . When STRB-N: is high,
and ILlR-N are also inputs to L2 field
STRR-P from the CPU INFIBUS access circuit
modification multiplexer U14.
is low which resets flip-flop FF3. The 1
output of FF3 (low) sets flip-flop FF3 which
5-249. Gates G1 through G4 decode M03S-P
enables gates G10 and G18.
M04S-P, MOSS-P, and M04R-N. Gl through
G3 determine which data is to be coupled
5-254. When the CPU address is on the
through M field modification multiplexer
INFIBUS address lines, BAO8-P and BA09-P
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