CPU EMULATION INSTRUCTION REGISTER CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

E11S-P is also routed to the CPU INFIBUS

5-235. CPU EMULATION INSTRUCTION

access circuit. When E12S-P and E13S-P,

from emulation register Ul are low, gate

5-236. General. The CPU emulation in-

Gl is activated generating DTOA-P which is

routed to the CPU control circuit.

struction register circuit modifies fields of

the microcode word stored in the CPU micro-

5-241. EOOS-P through E03S-P are also

code register circuit. It also stores data

routed to the CO through C3 inputs of the

from the CPU ALU circuit. This stored data

X field modification multiplexer U15. Also,

addresses the data tables which are com-

E04S-P through E07S-P are routed to the BO

prised of two ROM's. The outputs of the

through B3 inputs of the X field modification

data tables modify the M, Ll, and L2 fields

multiplexer U15. BAOl-P through BAO4-P

of the microcode word stored in the CPU

from the CPU address register circuit are

microcode register circuit.

routed through four spare INFIBUS lines,

between the CPA A1A3A7 and CPB A1A3A6,

5-237. Detail Analysis (see figure 23).

to the A0 through A3 inputs of the field

When the master reset pulse, MRES-N, is

modification multiplexer U15.

generated, the CPU control circuit generates

RST2-N which clears emulation registers Ul

and US and emulation register/counter U3.

5-242. The X field modification multiplexer

U15 selects one of the three groups of data

5-238. LBOO-P through LB15-P from the

(EOOS-P through E03S-P; E04S-P through

CPU ALU circuit are routed to the data inputs

E07S-P; or BAOl-P through BAO4-P) as

of emulaation registers U1 and US and emula-

determined by the levels of Ml8T-P and

tion register/counter U3. Emulation registers

M19T-P from the CPU microcode register

Ul and US are clocked by SETE-P from the

circuit. M18T-P and M19T-P are routed to

CPU control circuit which loads them with

the select inputs (SO and S1 of X field

LB04-P through LB15-P, as required. Emula-

modification multiplexer U15. When

tion register/counter U3 is loaded with

M18T-P and M19T-P are both low, gate G2

LBOO-P through LB03-P when the CPU con-

is disabled which disables X field modifi-

trol circuit generates LCLD-N which en-

cation multiplexer U15 and associated out-

ables the load (LD) input of emulation

puts (FO through F3) are all high.

ition of CKTR-N from the CPU central timing

5-243. When M18T-P is high, G2 is

control clocks the emulation register/

activated which enables X field modifica-

.counter U3.

tion multiplexer U15. Also, M18T-P causes

X field modification multiplexer U15 to

5-239. When the CPU control circuit gen-

couple EOOS-P through CO3S-P to the FO

erates TSE-IF-P, the emulation register/

through F3 outputs. UB20-P through

counter U3 is enabled to count by one on

UB23-P assume the logic levels of data

each low-to-high transition of CKTR-N.

EOOS-P through E03S-P and are routed to

Emulation register/counter U3 counts from

the CPU microcode register circuit to mod-

the preloadecd binary count (determined by

ify the X field of the microcode word.

LBOO-P through LB03-P) to binary 15 and

generates EMAX-P which is routed to the

5 - 2 4 4 . When M19T-P is high, G2 is acti-

CPU control circuit. On the sixteenth count

vated which enables X field modification

the emulation register/counter U3 resets to

multiplexer U15. Also, M19T-P causes

zero.

X field modification multiplexer U15 to

5 - 2 4 0 . Emulation registers Ul and U5 and

couple E04S-P through E07S-P to the FO

through F3 outputs. UB20-P through UB23-P

emulation register/counter U3 generate

assume the logic levels of data E04S-P

EOOS-P through E15S-P which are routed to

through E07S-P and are routed to the CPU

the table ROM address multipiexers U2 and

U4. E03S-P, E07S-P, E11S-P, and E14S-P

microcode register circuit to modify the X

are also routed to the CPU control circuit.

field of the microcode word.

5-35