CPU CONTROL CIRCUIT

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

5-171. Gates G2 through G4 and inverters

through M13S-P are routed from the CPU

13 and 14 decode inputs from the CPU micro-

microcode register circuit to the CPU se-

quence register and control storage circuit

code register circuit and CPU central timing

for decoding, M20S-P through M23S-P,

control circuit to enable the binary decoder

M22R-N, and M23R-N are routed from the

U32. When enabled, a binary-coded deci-

CPU microcode register circuit to the CPU

mal at the A0 through A2 inputs of binary

decoder U32 causes one of the seven out-

M26S-P, and M27S-P are routed to the CPU

puts to go low.

carry and overflow circuit, and M02T-P and

M32T-P are routed to the CPU central timing

5-l72. Gates G6 through G12 decode inputs

control circuit for decoding.

from the CPU microcode register which con-

trols the operation of the CPU address reg-

5-167. CPU CONTROL CIRCUIT.

ister circuit, CPU emulation instruction

5 - 1 6 8 . General. The CPU control circuit

cuit and the CPU carry and overflow circuit.

decodes portions of the microcode word

stored within the CPU microcode register

5-173

Data selector/multiplexer U47 de-

circuit to control the operation of the various

codes a binary-coded decimal at the A, B,

CPU circuits. The CPU control circuit con-

and C inputs and selects one of eight data

trols the following circuits: CPU sequence

inputs, DO through D7. Gates G13 and G14

decode inputs from the CPU microcode reg-

ister circuit and CPU control timing control

address register circuit, CPU emulation

circuit to preset flip-flop FFl.

instruction register circuit, CPU INFIBUS

access circuit, CPU carry and overflow cir-

cuit, CPU central timing control circuit,

5-174. Gates G16 through G18 decode in-

puts from the CPU microcode register circuit

CPU microcode register circuit, and the

CPU address recognition circuit,

to generate STAT-N to the Bus Controller.

5-175. Flip-flops FF3 and FF5 are the CPU

5 - 1 6 9 . Detail Analysis (see figure 15).

When the master reset pulse, MRES-N, is

control register. FF3 is the halt buffer and

generated on the INFIBUS, MRES-N is in-

FF5 is the run buffer. When FF3 is set,

verted by inverter 19 which generates

the CPU is in halt mode and when FF5 is

MRST-P. MRST-P disables data selector/

cleared the CPU is in the run mode (per-

multiplexer U47, and MRST-P is also routed

forming operations). FF4 is the ALU buffer

to the CPU INFIBUS access circuit. In-

and when FF4 is set by ALU1-P, ALU1 -P is

verters 17 and 18 invert MRST-P which gen-

generated when a comparison test performed

by the CPU ALU circuit is true. FF2 is the

erates RSTl-P and RST2-P, respectively.

interrupt buffer which is cleared when inter-

RSTl-P is routed to the CPU central timing

rupts are processed by the CPU.

control circuit and RST2-P is routed to the

CPU emulation instruction register circuit

and CPU INFIBUS access circuit. In addi-

5-176. Data selector/multiplexer U41 de-

codes the binary-coded decimal at A, B, C,

tion, RSTl-N resets flip-flops FF3 through

and D inputs which selects one of the four-

FF5.

teen inputs (EO through E12 and E14). The

selected input is inverted and coupled to

5-170. Data selector/multiplexer U48 de-

the W output which generates CNDT-N.

codes the binary-coded decimal at the A,

B and C inputs which selects one of the

eight data inputs (DO through D7). The

CPU RECEIVE REGISTER CIRCUIT.

5-177.

selected input IS coupled to the Y output of

data selector multiplexer U48 and the in-

5 - 1 7 8 . General. The CPU receive register

circuit Interfaces the CPU with the INFIBUS

verse of the selected input is coupled to

data lines for the bidirectional transfer of

the W output.

5-28